DS3112+W Maxim Integrated Products, DS3112+W Datasheet - Page 61

• Manufacturer Part Number: DS3112+W
• Description: IC MUX T3/E3 3.3V 256-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3112+W

• Controller Type: Framer, Multiplexer
• Interface: Parallel/Serial
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15: 16-Bit T3 C-Bit Parity Bit Error Counter (CPE0 to CPE15). These bits report the number of T3
C-bit parity bit errors. When the device is not in the C-bit parity mode or when the device is in the E3 mode, this
counter is meaningless and should be ignored. A C-bit parity bit error is defined as an occurrence when the
majority decoded three CP parity bits do not match the parity calculation made on the information bits. Via the
ECC control bit in the T3/E3 control register (Section 5.2), the CPCR can be configured to either continue counting
C-bit parity bit errors during a LOF or not.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15: 16-Bit T3 Far End Block Error or E3 RAI Counter (FEBE0 to FEBE15). In the T3 C-bit parity
mode, these bits report the number of T3 Far End Block Errors (FEBE). This counter increments each time the
three FEBE bits do not equal 111. In the E3 Mode, these bits report the number of times the RAI bit is received in
the “disturbed state” (i.e., the number of times that it is set to a one). In the T3 mode, when the device is not in the
C-bit parity mode, this counter is meaningless and should be ignored. Via the ECC control bit in the T3/E3 control
register (Section 5.2), the FEBECR can be configured to either continue counting FEBEs or active RAI bits during
a LOF or not.
FEBE15
FEBE7
CPE15
CPE7
—
15
—
—
15
—
7
7
FEBE14
FEBE6
CPE14
CPE6
—
14
—
—
14
—
6
6
CPCR
T3 C-Bit Parity Bit Error Count Register
28h
FEBECR
T3 Far End Block Error or E3 RAI Count Register
2Ah
FEBE13
FEBE5
CPE13
CPE5
—
13
—
—
13
—
5
5
FEBE12
FEBE4
61 of 133
CPE12
CPE4
—
12
—
—
12
—
4
4
FEBE11
FEBE3
CPE11
CPE3
—
11
—
—
11
—
3
3
FEBE10
FEBE2
CPE10
CPE2
—
10
—
—
10
—
2
2
FEBE1
FEBE9
CPE1
CPE9
—
—
—
—
1
9
1
9
FEBE0
FEBE8
CPE0
CPE8
—
—
—
—
DS3112
0
8
0
8