DS3112+W Maxim Integrated Products, DS3112+W Datasheet - Page 40

• Manufacturer Part Number: DS3112+W
• Description: IC MUX T3/E3 3.3V 256-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3112+W

• Controller Type: Framer, Multiplexer
• Interface: Parallel/Serial
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

determine the change of state. This bit will be cleared when the BERTEC0 is read and will not be set again until
the BERT has experienced another change of state. The setting of this status bit can cause a hardware interrupt to
occur if the BERT bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed
to clear when the BERTEC0 register is read
Bit 3: Change in HDLC Status (HDLC). This read-only real-time status bit will be set to a one if there is a
change of status in the HDLC controller and the associated interrupt enable bit is set in the IHSR register. The host
must read the status bits of the HDLC in the HDLC Status Register (HSR) to determine the change of state. This bit
will be cleared when the HSR is read and will not be set again until the HDLC has experienced another change of
state. The setting of this status bit can cause a hardware interrupt to occur if the HDLC bit in the Interrupt Mask for
MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when the HSR register is read
(see
Bit 4: Change in FEAC Status (FEAC). This read-only real-time status bit will be set to a one when the FEAC
controller has detected and verified a new Far End Alarm and Control (FEAC) 16-bit codeword. This bit will be
cleared when the FEAC Status Register (FSR) is read and will not be set again until the FEAC controller has
detected and verified another new codeword. The setting of this status bit can cause a hardware interrupt to occur if
the FEAC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear
when the FSR register is read.
Bit 5: Change in T2/E2 LOF or AIS Status (T2E2SR1). This read-only real-time status bit will be set to a one
when one or more of the T2/E2/G.747 framers have detected a change in either Loss Of Frame (LOF) or Alarm
Indication Signal (AIS) and the associated interrupt enable bit is set in the T2E2SR1 register. See the T2E2SR1
register description in Section
setting of this status bit can cause a hardware interrupt to occur if the T2E2SR1 bit in the Interrupt Mask for MSR
(IMSR) register is set to a one. The interrupt will be allowed to clear when the T2E2SR1 register is read (see
Figure
Bit 6: Change in T2/E2 RAI Status (T2E2SR2). This read-only real-time status bit will be set to a one when one
or more of the T2/E2/G.747 framers have detected a change in the detection of the Remote Alarm Indication (RAI)
signal and the interrupt enable (bit 7) is set in the T2E2SR2 register. See the T2E2SR2 register description in
Section
bit can cause a hardware interrupt to occur if the T2E2SR2 bit in the Interrupt Mask for MSR (IMSR) register is set
to a one. The interrupt will be allowed to clear when the T2E2SR2 register is read (see
Bit 8: T1 Loopback Detected (T1LB). This read-only real-time status bit will be set to a one when one or more of
the T2 framers have detects an active T1 loopback command. See the T1LBSR1 and T1LBSR2 register
descriptions in Section
active on any of the lines. The setting of this status bit can cause a hardware interrupt to occur if the T1LB bit in
the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when the none of
the T2 framers detects an active T1 loopback command (see
Bit 9: Change in T3/E3 Framer Status (T3E3SR). This read-only real-time status bit will be set to a one when
the T3/E3 framer has detected a change in RAI, AIS, LOF, LOS, or T3 Idle signal or has detected the start of a
Transmit or Receive Frame and the associated interrupt enable bit is set in the T3E3SR register. See the T3E3SR
register description in Section
setting of this status bit can cause a hardware interrupt to occur if the T3E3SR bit in the Interrupt Mask for MSR
(IMSR) register is set to a one. The interrupt will be allowed to clear when the T3E3SR register is read (see
Figure
Bit 10: Loss Of Transmit Clock Detected (LOTC). This read-only real-time status bit will be set to a one when
the device detects that the FTCLK clock has not toggled for 200ns (±100ns). This bit will be cleared when a clock
is detected at the FTCLK input. The setting of this status bit can cause a hardware interrupt to occur if the LOTC
bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when the
Figure
4-6).
4-9).
6.3
4-5).
for more details. This bit will be cleared when the T2E2SR2 register is read. The setting of this status
7.3
for more details. This bit will be cleared when the T1 loopback command is no longer
6.3
5.3
for more details. This bit will be cleared when the T2E2SR1 register is read. The
for more details. This bit will be cleared when the T3E3SR register is read. The
(Figure
4-4).
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Figure
4-8).
Figure
4-7).
DS3112