DS3112+W Maxim Integrated Products, DS3112+W Datasheet - Page 39

• Manufacturer Part Number: DS3112+W
• Description: IC MUX T3/E3 3.3V 256-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3112+W

• Controller Type: Framer, Multiplexer
• Interface: Parallel/Serial
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 4-3. Real-Time Status Bit
4.3.2 MSR
The Master Status Register (MSR) is a special status register that can be used to help the host quickly
locate changes in device status. There is a status bit in the MSR for each of the major blocks within the
DS3112. When an alarm or event occurs in one of these blocks, the device can be configured to set a bit
in the MSR. Status bits in the MSR can also cause a hardware interrupt to occur. In either polled or
interrupt driven software routines, the host can first read the MSR to locate which status registers need to
be serviced.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: One-Second Timer Boundary Occurrence (OST). This latched read-only event-status bit will be set to a
one on each one-second boundary as timed by the DS3112. The device chooses an arbitrary one-second boundary
that is timed from the HRCLK signal. This bit will be cleared when read and will not be set again until another
one-second boundary has occurred. The setting of this status bit can cause a hardware interrupt to occur if the OST
bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this
bit is read.
Bit 1: Counter Overflow Event (COVF). This latched read-only event-status bit will be set to a one if any of the
error counters saturates (the error counters saturate when full). This bit will be cleared when read even if one or
more of the error counters is still saturated. The setting of this status bit can cause a hardware interrupt to occur if
the COVF bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear
when this bit is read.
Bit 2: Change in BERT Status (BERT). This read-only real-time status bit will be set to a one if there is a major
change of status in the BERT receiver and the associated interrupt enable bit is set in the BERTCO register. A
major change of status is defined as either a change in the receive synchronization (i.e., the BERT has gone into or
out of receive synchronization), a bit error has been detected, or an overflow has occurred in either the Bit Counter
or the Error Counter. The host must read the status bits of the BERT in the BERT Status Register (BERTEC0) to
Internal Signal
Status Bit
Interrupt
Read
—
—
15
—
—
7
T2E2SR2
—
14
—
—
6
MSR
Master Status Register
08h
T2E2SR1
G.747
—
13
—
5
—
T3E3MS
39 of 133
FEAC
12
—
4
—
HDLC
LORC
11
—
3
—
BERT
LOTC
10
—
2
—
T3E3SR
COVF
—
1
9
—
T1LB
OST
—
DS3112
0
8