DS3112 Maxim Integrated Products, DS3112 Datasheet
DS3112
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DS3112 Summary of contents
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... Routers Optical Multiplexers ADMs Test Equipment ORDERING INFORMATION PART DS3112 DS3112+ DS3112N DS3112N+ +Denotes lead-free/RoHS-compliant package 133 DS3112 T2/E2 T3/E3 DS3112 T2/E2 TEMP RANGE PIN-PACKAGE 256 PBGA 0°C to +70°C 256 PBGA 0°C to +70°C 256 PBGA -40°C to +85°C 256 PBGA -40° ...
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... DETAILED DESCRIPTION 1 PPLICABLE TANDARDS 1.2 M DS3112 TEMPE F AIN 1.2.1 General Features ................................................................................................................................... 9 1.2.2 T3/E3 Framer ......................................................................................................................................... 9 1.2.3 T2/E2 Framer ......................................................................................................................................... 9 1.2.4 HDLC Controller..................................................................................................................................... 9 1.2.5 FEAC Controller ..................................................................................................................................... 9 1.2.6 BERT.................................................................................................................................................... 10 1.2.7 Diagnostics........................................................................................................................................... 10 1.2.8 Control Port .......................................................................................................................................... 10 1.2.9 Packaging and Power .......................................................................................................................... 10 2 PIN DESCRIPTION 2.2 CPU IGNAL ESCRIPTION 2 ...
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... IT ARITY ODE OMMAND TATUS EGISTER ESCRIPTION ONTROL EGISTER ESCRIPTION ..................................................................................................78 ..................................................................................................................87 ................................................................................................................87 FIFO R D EGISTER ESCRIPTION R D NTERRUPT EGISTER ESCRIPTION D ...................................................................................96 ESCRIPTION D ......................................................................................98 ESCRIPTION M D ....................................................................100 TATE ACHINE ESCRIPTION I .............................................................................103 NSTRUCTIONS ...........................................................................................................121 .........................................................................................................123 .........................................................................................................125 3 of 133 .................................................75 ......................................................76 ..................................................................88 .............................................................91 DS3112 109 110 121 ...
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... E13 B .............................................................................................................................128 ASICS 14 RAMING TRUCTURE AND 14. RAMING TRUCTURE AND 14.11 G.747 B ......................................................................................................................131 ASICS 14.12 G.747 F S RAMING 15 PACKAGE INFORMATION 15.1 256-B PBGA (56-G6002-001)............................................................................................133 ALL E12 M ....................................................................129 ULTIPLEXING E23 M ULTIPLEXING E12 M TRUCTURE AND ULTIPLEXING 4 of 133 ................................................................129 ...........................................................132 DS3112 133 ...
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... Figure 1-1. DS3112 Framer and Multiplexer Block Diagram (T3 Mode) ................................................................... 11 Figure 1-2. DS3112 Framer and Multiplexer Block Diagram (E3 Mode)................................................................... 12 Figure 1-3. DS3112 Framer and Multiplexer Block Diagram (G.747 Mode) ............................................................. 13 Figure 2-1. T3/E3 Receive Framer Timing ................................................................................................................ 22 Figure 2-2. T3/E3 Transmit Formatter Timing ........................................................................................................... 24 Figure 4-1. Event Status Bit....................................................................................................................................... 38 Figure 4-2 ...
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... Table 14-1. T Carrier Rates ..................................................................................................................................... 122 Table 14-2. T2 Overhead Bit Assignments.............................................................................................................. 123 Table 14-3. T3 Overhead Bit Assignments.............................................................................................................. 125 Table 14-4. C-Bit Assignment for C-Bit Parity Mode ............................................................................................... 126 Table 14-5. E Carrier Rates..................................................................................................................................... 128 Table 14-6. G.747 Carrier Rates ............................................................................................................................. 131 LIST OF TABLES 6 of 133 DS3112 ...
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... DETAILED DESCRIPTION The DS3112 TEMPE (T3 E3 MultiPlexEr) device can be used either as a multiplexer or a T3/E3 framer. When the device is used as a multiplexer, it can be operated in one of three modes: M13—Multiplex 28 T1 lines into a T3 data stream E13—Multiplex 16 E1 lines into an E3 data stream G.747— ...
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... Equipment Operating at the Primary Rate And Above” 19) International Telecommunication Union (ITU) O.153, October 1992 “Basic Parameters for the Measurement of Error Performance at Bit Rates Below the Primary Rate” 20) International Telecommunication Union (ITU) O.161, 1984 “In-Service Code Violation Monitors for Digital Systems” 133 DS3112 ...
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... Main DS3112 TEMPE Features 1.2.1 General Features Can be operated as a standalone framer without any M13 or E13 multiplexing T1/E1 FIFOs in the receive direction provide T1/E1 demultiplexed clocks with very little jitter Two T1/E1 drop and insert ports B3ZS/HDB3 encoder and decoder ...
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... M or FAS), EXcessive Zeros (EXZ), T3 Parity bits, T3 C-Bit Parity, and Far End Block Errors (FEBE) Error counters can be either updated automatically on one second boundaries as timed by the DS3112 or via software control or via an external hardware pulse Can insert the following T3/E3 errors: BiPolar Violations (BPV), EXcessive Zeros (EXZ), T3 Parity ...
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... Figure 1-1. DS3112 Framer and Multiplexer Block Diagram (T3 Mode) T3 Formatter T3 Framer Error Counters CA0 to CD0 to CWR* FRMECU CA7 CD15 (CR/W*) Signal HRCLK Inversion Loss Of Transmit Clock Control Mux Mux Sync T2 Control For- 1 matter 2 BERT Mux 7 Transmit BERT HDLC Controller with 256 Byte ...
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... Figure 1-2. DS3112 Framer and Multiplexer Block Diagram (E3 Mode) E3 Formatter E3 Framer Error Counters CA0 to CD0 to CWR* FRMECU CA7 CD15 (CR/W*) Signal HRCLK Inversion Loss Of Transmit Clock Control Mux Mux Sync E2 Control For- 1 matter 2 3 BERT Mux 4 Transmit BERT HDLC Controller with 256 Byte ...
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... Figure 1-3. DS3112 Framer and Multiplexer Block Diagram (G.747 Mode) T3 Formatter T3 Framer Error Counters FRMECU CA0 to CD0 to CWR* CA7 CD15 (CR/W*) Signal HRCLK Inversion Loss Of Transmit Clock Control Mux Mux Sync G747 Control For- 1 matter 2 BERT Mux 7 Transmit BERT HDLC Controller ...
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... PIN DESCRIPTION This section describes the input and output signals on the DS3112. Signal names follow a convention that is shown in Table 2-1. Table 2-2 Table 2-1. Pin Naming Convention FIRST SIGNAL CATEGORY LETTERS C CPU/Host Control Access Port FR T3/E3 Receive Framer FT T3/E3 Transmit Formatter ...
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... Low-Speed (T1 or E1) Receive Clock from Port 9 O Low-Speed (T1 or E1) Receive Clock from Port 10 O Low-Speed (T1 or E1) Receive Clock from Port 11 O Low-Speed (T1 or E1) Receive Clock from Port 12 O Low-Speed (T1 or E1) Receive Clock from Port 13 O Low-Speed (T1 or E1) Receive Clock from Port 133 DS3112 FUNCTION ...
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... Low-Speed (T1 or E1) Receive Data from Port 25 O Low-Speed (T1 or E1) Receive Data from Port 26 O Low-Speed (T1 or E1) Receive Data from Port 27 O Low-Speed (T1 or E1) Receive Data from Port 28 O Low-Speed (T1 or E1) Receive Data from Drop Port A O Low-Speed (T1 or E1) Receive Data from Drop Port 133 DS3112 FUNCTION ...
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... Low-Speed (T1 or E1) Transmit Data for Port 10 I Low-Speed (T1 or E1) Transmit Data for Port 11 I Low-Speed (T1 or E1) Transmit Data for Port 12 I Low-Speed (T1 or E1) Transmit Data for Port 13 I Low-Speed (T1 or E1) Transmit Data for Port 14 I Low-Speed (T1 or E1) Transmit Data for Port 133 DS3112 FUNCTION ...
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... Low-Speed (T1 or E1) Transmit Data for Insert Port A I Low-Speed (T1 or E1) Transmit Data for Insert Port B — No Connection. Do not connect any signal to this pin. I Active-Low Reset I T3/E3 Mode Select T3 Active-Low Factory Test Input 3.3V (±5%) Positive Supply — Ground Reference 18 of 133 DS3112 FUNCTION ...
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... Signal Description: CPU Bus Read Enable (CPU Bus Data Strobe) Signal Type: Input In Intel Mode (CIM = 0) this signal will determine when data read from the device. In Motorola Mode (CIM = 1), a rising edge will be used to write data into the device 133 DS3112 ...
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... This input signal controls a latch that exists on the CA0 to CA7 inputs. When CALE is high, the latch is transparent. The falling edge of CALE causes the latch to sample and hold the CA0 to CA7 inputs. In nonmultiplexed bus applications, CALE should be tied high. In multiplexed bus applications, CA[7:0] should be tied to CD[7:0] and the falling edge of CALE will latch the address 133 DS3112 ...
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... Signal Type: Input Via the AECU control bit in Master Control Register 1 (Section 4.3), the DS3112 can be configured to use this asynchronous input to initiate an updating of the internal error counters. A zero to one transition on this input causes the device to begin loading the internal error counters with the latest error counts. ...
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... FRDEN Gapped Clock Mode for T3 (see note) FRDEN Gapped Clock Mode for E3 (see note) FRSOF (see note) NOTE: FRD, FRDEN, AND FRSOF CAN BE INVERTED VIA MASTER CONTROL REGISTER 3. Last Bit of T3: X1 the Frame E3: Bit 1 of FAS 22 of 133 DS3112 ...
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... This signal can be internally inverted if enabled via the FTDENI control bit in Master Control Register 3 (Section 4.2). This signal operates in the same manner even when the device is configured in the Transmit Pass Through mode (see the TPT control bit in the T3/E3 Control Register 133 DS3112 ...
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... Signal Type: Input Via the EIC control bit in the T3/E3 Error Insert Control Register (Section 5.2), the DS3112 can be configured to use this asynchronous input to cause errors to be inserted into the transmitted data stream. A zero to one transition on this input causes the device to begin the process of causing errors to be inserted ...
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... LRCLK. This option is controlled via the LRCLKI control bit in Master Control Register 2 (Section 4.2). When the M13/E13 multiplexer is disabled, then these outputs are meaningless and should be ignored 133 DS3112 ...
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... LTCLK17 to LTCLK28 are meaningless and should be tied low. When the device is in the G.747 Mode, LTCLK4, LTCLK8, LTCLK12, LTCLK16, LTCLK20, LTCLK24, and LTCLK28 are meaningless and should be tied low. When the M13/E13 multiplexer is disabled, then these inputs are ignored and should be tied low 133 DS3112 ...
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... E3 mode, LTCCLK would be 2.048MHz. If not used, this signal should be tied low. If this signal is used, then all of the LTCLK signals should be tied low. This signal can be internally inverted. This option is controlled via the LTCLKI control bit in Master Control Register 2 (Section 4.2 133 DS3112 ...
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... This output signal is used to clock data out of the device. The serial data streams at the HTPOS and HTNEG signals can be clocked out of the device either on rising edges (normal clock mode) or falling edges (inverted clock mode) of HTCLK. This option is controlled via the HTCLKI control bit in Master Control Register 2 (Section 4.2 133 DS3112 ...
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... T1/E1 ports to source an unframed all ones data pattern. The device will be held in a reset state as long as this signal is low. This signal should be activated after the hardware configuration signals (LIEN and T3E3MS) and the clocks (FTCLK, LTCLK, HRCLK, and LITCLK) are stable and must be returned high before the device can be configured for operation 133 DS3112 ...
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... Signal Type: Input This signal determines whether the DS3112 will operate in either the T3 mode or the E3 mode. It acts as a global control bit for the entire DS3112. This signal should be set into the proper state before a hardware reset is issued via the RST signal. This input is coupled with the G.747E input to create a special test ...
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... BERT Repetitive Pattern Set 1 (upper word) R BERT Bit Counter 0 (lower word) R BERT Bit Counter 1 (upper word) R BERT Error Counter 0 (lower word) R BERT Error Counter 1 (upper word) HDLC Control Register 31 of 133 DS3112 SECTION 4.1 4.2 4.2 4.2 4.3 4.3 4.4 5.2 5.3 5 ...
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... Addresses are not assigned. REGISTER NAME R Receive HDLC FIFO Register W Transmit HDLC FIFO Register R HDLC Status Register Interrupt Mask Register for HSR FEAC Control Register R FEAC Status Register — Not Assigned 32 of 133 DS3112 SECTION 9.2 9.2 9.3 9.3 10.1 10.2 * ...
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... Bit 1: Low-Speed (T1/E1) Receive FIFO Reset (RFIFOR). A zero to one transition on this bit will cause the receive T1/E1 demux FIFOs to be reset, which will cause them to be flushed. See the DS3112 Block Diagrams in Figure 1-1 ...
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... LTDAT inputs are ignored. The table below displays which bits are not sampled at the FTD input when UNCHEN = enable the M13/E13/G.747 multiplexers and disable the FTD Input 1 = disable the M13/E13/G.747 multiplexers and enable the FTD Input DS3112 MODE T3 M23 (C-Bit Parity Disabled) T3 C-Bit Parity E3 Bit 2: T3 C-Bit Parity Mode Enable (CBEN) ...
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... Bit 6: Loss Of Transmit Clock Mux Control (LOTCMC). The DS3112 can detect if the FTCLK fails to transition. If this bit is set low, the device will take no action (other than setting the LOTC status bit) when the FTCLK fails to transition. When this bit is set high, the device will automatically switch to the input receive clock (HRCLK) when the FTCLK fails and transmit AIS ...
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... Bit 11: LRDAT Invert Enable (LRDATI not invert the LRDAT[n], LRDATA and LRDATB signals (normal mode invert the LRDAT[n], LRDATA and LRDATB signals (inverted mode) MC2 Master Configuration Register 2 04h HTDATL HTDATH HRDATI — — LRDATI — — 133 DS3112 HRCLKI HTDATI HTCLKI LRCLKI LTDATI LTCLKI ...
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... Bit 7: FRSOF Invert Enable (FRSOFI not invert the FRSOF signal (normal mode invert the FRSOF signal (inverted mode) MC3 Master Configuration Register 3 06h 5 4 FRDI FRDENI FTSOFI — — — — 133 FTCLKI FTDI — — — — — — DS3112 0 FTDENI 0 8 — — ...
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... There are three types of status bits in the DS3112. The first type is called an event status bit and is derived from a momentary condition or state that occurs within the device. The event status bits are always cleared when read and can generate an interrupt when they are asserted ...
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... There is a status bit in the MSR for each of the major blocks within the DS3112. When an alarm or event occurs in one of these blocks, the device can be configured to set a bit in the MSR. Status bits in the MSR can also cause a hardware interrupt to occur. In either polled or interrupt driven software routines, the host can first read the MSR to locate which status registers need to be serviced ...
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... Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when the (Figure 4-4). for more details. This bit will be cleared when the T2E2SR1 register is read. The Figure for more details. This bit will be cleared when the T3E3SR register is read. The 40 of 133 Figure 4-7). 4-8). DS3112 ...
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... NOTE: ALL EVENT AND ALARM LATCHES ABOVE ARE CLEARED WHEN THE BERTEC0 REGISTER IS READ. RLOS (BERTEC0 Bit 4) Event Latch Mask IESYNC (BERTC0 Bit 15) BED (BERTEC0 Bit 3) Mask IEBED (BERTC0 Bit 14) BECO or BBCO (BERTEC0 Bits 1 & 2) Mask IEOF (BERTC0 Bit 13 133 BERT OR Status Bit (MSR Bit 2) INT* Mask Hardware Signal BERT (IMSR Bit 2) DS3112 ...
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... TUDR Event Latch (HSR Bit 7) Mask TUDR (IHSR Bit 3) ROVR Event Latch (HSR Bit 13) Mask ROVR (IHSR Bit 13) RABT Event Latch (HSR Bit 15) Mask RABT (IHSR Bit 15 133 HDLC OR Status Bit (MSR Bit 3) INT* Mask Hardware Signal HDLC (IMSR Bit 3) DS3112 ...
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... LOF7 Bit 7) (T2E2SR1 Bit 6) Event Latch OR AIS1 (T2E2SR1 Bit 8) Event Latch AIS2 (T2E2SR1 Bit 9) Event Latch OR Mask IEAIS (T2E2SR1 AIS7 Bit 15) (T2E2SR1 Bit 14) Event Latch 43 of 133 DS3112 T2E2SR1 Status Bit (MSR Bit 5) INT* Mask Hardware Signal T2E2SR1 (IMSR Bit 5) ...
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... Bit 7) (T2E2SR2 Bit 6) Event Latch LLB1 (T1LBSR1 Bit 0) LLB2 (T1LBSR1 Bit 1) OR LLB28 (T1LBSR2 Bit 11) T1LB (IMSR Bit 133 DS3112 T2E2SR2 Status Bit (MSR Bit 6) INT* Mask Hardware Signal T2E2SR2 (IMSR Bit 6) T1LB Status Bit (MSR Bit 8) INT* Mask Hardware Signal ...
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... Mask OR AIS (IT3E3SR Bit 3) T3IDLE (T3E3SR Bit 4) Event Latch Mask T3IDLE (IT3E3SR Bit 4) RSOF (T3E3SR Bit 5) Mask RSOF (IT3E3SR Bit 5) TSOF (T3E3SR Bit 6) Mask TSOF (IT3E3SR Bit 133 DS3112 T3E3SR Status Bit (MSR Bit 9) INT* Mask Hardware Signal T3E3SR (IMSR Bit 9) ...
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... Bit 10: Loss Of Transmit Clock (LOTC interrupt masked 1 = interrupt unmasked Bit 11: Loss Of Receive Clock (LORC interrupt masked 1 = interrupt unmasked IMSR Interrupt Mask for Master Status Register 0Ah 5 4 T2E2SR1 FEAC HDLC — — — — 133 BERT COVF LORC LOTC T3E3SR DS3112 0 OST 0 8 T1LB 0 ...
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... Default — — Bits Factory Test Bits (FT0 to FT5). These bits are used by the factory to place the DS3112 into the test mode. For normal device operation, these bits should be set to zero whenever this register is written to. TEST Test Register 0Ch ...
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... When this loopback is enabled, the incoming receive data continues to pass through the device but the data normally being input to the T3/E3 formatter is ignored. See the block diagrams in Section for a visual description of this loopback. 1 for a visual description of this loopback. Please note that the 48 of 133 DS3112 1 for a visual 1 ...
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... T3E3CR T3/E3 Control Register 10h 5 4 T3IDLE E3SnC1 E3SnC0 TFEBE AFEBED ECC 0 0 SOURCE OF THE E3 NATIONAL BIT (Sn) Figure 1-1 and 49 of 133 TPT TRAI FECC1 FECC0 Figure 1-2 for a visual description of this DS3112 0 TAIS 0 8 E3CVE 0 ...
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... FEBE to 111 (null state force FEBE to 000 (active state) Bit 14: T3/E3 Payload Loopback Enable (PLB). See loopback disable loopback 1 = enable loopback Figure 1-1 and Figure 1-2 for a visual description of this Figure 1-1 and Figure 1-2 for a visual description of this 50 of 133 DS3112 ...
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... P bits.) Once this bit has been toggled from a 14.7 for details about the CP bits.) Once this bit has been 14.7 for details about the C-Bit Parity mode.) or when the device 133 T3PBEI EXZI — — — — — — DS3112 0 BPVI 0 8 — — 4.2 ...
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... FBEI control bits are set to zero, no errors are inserted use zero to one transition on the BPVI, EXZI, T3PBEI, T3CPBEI, or FBEI control bits to insert errors 1 = use zero to one transition on the FTMEI input signal to insert errors TYPE OF FRAMING BIT ERROR INSERTED 52 of 133 DS3112 ...
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... T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The IDLE detection criteria are described in bit is read. When the DS3112 is operated in the E3 mode, this status bit should be ignored. Bit 5: Transmit T3/E3 Start Of Frame (TSOF). This latched read-only event-status bit will be set to a one on each T3/E3 transmit frame boundary ...
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... Change in State Detect Event Latch Mask T3IDLE (IT3E3SR Bit 4) TSOF Event Latch (T3E3SR Bit 5) Mask TSOF (IT3E3SR Bit 5) RSOF Event Latch (T3E3SR Bit 6) Mask RSOF (IT3E3SR Bit 133 DS3112 T3E3SR Status Bit OR (MSR Bit 9) INT* Mask Hardware Signal T3E3SR (IMSR Bit 9) ...
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... Bit 6: Receive T3/E3 Start Of Frame (RSOF interrupt masked 1 = interrupt unmasked IT3E3SR Interrupt Mask for T3/E3 Status Register 14h 5 4 TSOF T3IDLE — — — — 133 RAI AIS LOF — — — — — — DS3112 0 LOS 0 8 — — ...
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... C bits in Subframe 3 are majority decoded to be zero during this time 133 DS3112 CLEAR CRITERIA In each 84 bit information field, the properly aligned 10... pattern is detected with 4 or more bit errors (out of 84 possible) for 1024 consecutive information bit fields (1 ...
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... B3ZS/HDB3 codeword. Bit 2: F-Bit or FAS Error Detected (FBE). This latched read-only status bit will be set to a one when the DS3112 has detected an error in either the F bits (T3 mode) or the FAS word (E3 mode). This bit will be cleared when read and will not be set again until the device detects another error ...
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... Bit 5: Severely Errored Framing Event Detected (SEFE). This latched read-only event-status bit will be set to a one each time the DS3112 has detected either three or more F bits in error out of 16 consecutive F bits (T3 mode) or four bad FAS words in a row (E3 mode). This bit will be cleared when read and will not be set again until the device detects another SEFE event ...
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... T3/E3 Performance Error Counters There are six error counters in the DS3112. All of the errors counters are 16 bits in length. The host has three options as to how these errors counters are updated. The device can be configured to automatically update the counters once a second or manually via either an internal software bit (MECU external signal (FRMECU) ...
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... PE5 PE4 PE3 — — PE13 PE12 PE11 — — 133 FE3 FE2 FE1 — — — FE10 FE9 — — — PE2 PE1 — — — PE10 PE9 — — — DS3112 0 FE0 — 8 FE8 — 0 PE0 — 8 PE8 — ...
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... FEBE5 FEBE4 FEBE3 — — FEBE13 FEBE12 FEBE11 — — 133 CPE2 CPE1 — — — CPE10 CPE9 — — — FEBE2 FEBE1 — — — FEBE10 FEBE9 — — — DS3112 0 CPE0 — 8 CPE8 — 0 FEBE0 — 8 FEBE8 — ...
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... AIS for T1 and E1 signals is defined as an unframed all ones pattern. On reset, the DS3112 will force AIS in both the transmit and receive directions on all 28 T1 and 16/21 E1 data streams the host’s task to configure the device to pass normal traffic via the T1E1RAIS1, T1E1RAIS2, T1E1TAIS1, and T1E1TAIS2 registers (Section 6 ...
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... G.747 modes. The received Sn can be read from the T2E2 Status Register force the Sn bit to zero 1 = force the Sn bit to one T2E2CR2 T2/E2 Control Register 2 32h 5 4 LOFG6 LOFG5 LOFG4 — — E2Sn4 — — FRAMING ERRORS GENERATED 63 of 133 LOFG3 LOFG2 E2Sn3 E2Sn2 — — — DS3112 0 LOFG1 0 8 E2Sn1 — ...
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... In the E3 mode, LOF5 to LOF7 (bits are (Figure 6-1). The interrupt will be allowed to clear when this bit is read. The Table 6-1, Table 6-2, and Table 64 of 133 LOF3 LOF2 - - - AIS4 AIS3 AIS2 - - - 6-3. In the E3 mode, AIS5 to AIS7 (bits DS3112 0 LOF1 - 8 AIS1 - ...
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... LOF7 Bit 7) (T2E2SR1 Bit 6) Event Latch OR AIS1 (T2E2SR1 Bit 8) Event Latch AIS2 (T2E2SR1 Bit 9) Event Latch OR Mask IEAIS (T2E2SR1 AIS7 Bit 15) (T2E2SR1 Bit 14) Event Latch 65 of 133 DS3112 T2E2SR1 Status Bit (MSR Bit 5) INT* Mask Hardware Signal T2E2SR1 (IMSR Bit 5) ...
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... RAI4 RAI3 RAI2 — — — E2Sn4 E2Sn3 E2Sn2 — — — 6-3. In the E3 mode, RAI5 to RAI7 (bits T2E2SR2 Mask Status Bit (MSR Bit 6) INT* Mask IERAI Hardware (T2E2SR2 Signal Bit 7) T2E2SR2 (IMSR Bit 6) DS3112 0 RAI1 — 8 E2Sn1 — ...
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... Four or fewer zeros in each of two consecutive 840-bit frames Four consecutive bad FAS Bit 1 of Set for four consecutive frames (3360 bits 133 DS3112 CLEAR CRITERIA Nine or more zeros in four consecutive M frames (4704 bits) Synchronization occurs for four consecutive M frames (4704 bits) ...
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... T1/E1 AIS Generation Control Registers to allow normal T1/E1 traffic to traverse the DS3112. See the block diagrams in Section flow. When the M13/E13 multiplexer function is disabled in the DS3112 (see the UNCHEN control bit in the Master Control Register 1 in Section meaningless and can be set to any value. ...
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... AIS14 AIS13 0 0 T1E1TAIS2 T1/E1 Transmit Path AIS Generation Control Register 2 46h 5 4 AIS22 AIS21 — — — — 133 AIS4 AIS3 AIS2 AIS12 AIS11 AIS10 AIS20 AIS19 AIS18 AIS28 AIS27 AIS26 DS3112 0 AIS1 0 8 AIS9 0 0 AIS17 0 8 AIS25 0 ...
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... G.747 mode is enabled, the T1 line loopback command functionality is not applicable. 7.4 T1/E1 Drop and Insert The DS3112 has the ability to drop any of the 16/21 E1 receive channels to either one of two drop ports. Drop Port A and Drop Port B consist of the outputs LRCLKA/LRDATA and LRCLKB/LRDATB, respectively ...
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... LLB22 LLB21 LLB20 — — LLB28 — — 1 for a visual description of this loopback. LLB1 71 of 133 LLB4 LLB3 LLB2 LLB11 LLB10 for a visual description of this loopback. LLB1 LLB19 LLB18 LLB27 LLB26 DS3112 0 LLB1 0 8 LLB9 0 0 LLB17 0 8 LLB25 0 ...
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... T1/E1 Diagnostic Loopback Control Register 2 56h 5 4 DLB22 DLB21 DLB20 — — DLB28 — — 133 DLB4 DLB3 DLB2 DLB11 DLB10 for a visual description of this DLB19 DLB18 DLB27 DLB26 for a visual description of this DS3112 0 DLB1 0 8 DLB9 0 0 DLB17 0 8 DLB25 0 ...
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... T1/E1 Port 2, and so on. These bits are meaningless in the E3 and G.747 modes and should be set not generate the line loopback command by inverting the C3 bit 1 = generate the line loopback command by inverting the C3 bit T1LBCR1 T1 Line Loopback Command Register 1 58h 5 4 LB6 LB5 LB14 LB13 LB12 133 LB4 LB3 LB2 LB11 LB10 DS3112 0 LB1 0 8 LB9 0 ...
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... C3 bit 1 = generate the line loopback command by inverting the C3 bit T1LBCR2 T1 Line Loopback Command Register 2 5Ah 5 4 LB22 LB21 — — — — 133 LB20 LB19 LB18 LB28 LB27 LB26 DS3112 0 LB17 0 8 LB25 0 ...
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... LLB22 LLB21 LLB20 — — — — LLB28 — — 133 LLB4 LLB3 LLB2 — — — LLB11 LLB10 — — — LLB19 LLB18 — — — LLB27 LLB26 — — — DS3112 0 LLB1 — 8 LLB9 — 0 LLB17 — 8 LLB25 — ...
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... Port 22 Port 15 10111 Port 133 T1LB Status Bit (MSR Bit 8) INT* Mask Hardware Signal T1LB (IMSR Bit DPAS2 DPAS1 DPBS2 DPBS1 11000 Port 24 11001 Port 25 11010 Port 26 11011 Port 27 11100 Port 28 11101 No Port 11110 No Port 11111 No Port DS3112 0 DPAS0 0 8 DPBS0 0 ...
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... Port 14 10110 Port 15 10111 77 of 133 IPAS3 IPAS2 IPAS1 IPBS3 IPBS2 IPBS1 Port 16 11000 Port 24 Port 17 11001 Port 25 Port 18 11010 Port 26 Port 19 11011 Port 27 Port 20 11100 Port 28 Port 21 11101 No Port Port 22 11110 No Port Port 23 11111 No Port DS3112 0 IPAS0 0 8 IPBS0 0 ...
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... Port 25 11010 Port 26 11011 Port 27 11100 Port 28 11101 T3/E3 Framer (payload bits only) 11110 T3/E3 Framer (payload + overhead bits) 11111 Illegal State 78 of 133 and Figure 1-2 for a visual description RBPS3 RBPS2 RBPS1 TBPS3 TBPS2 TBPS1 DS3112 0 RBPS0 0 8 TBPS0 0 ...
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... Port 9 01010 Port 10 01011 Port 11 01100 Port 12 01101 Port 13 01110 Port 14 01111 Port 15 11000 Port 24 11001 Port 25 11010 Port 26 11011 Port 27 11100 Port 28 11101 T3/E3 Framer (payload bits only) 11110 T3/E3 Framer (payload + overhead bits) 11111 Illegal State 79 of 133 DS3112 ...
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... PS[2:0] select a pattern from Pattern Bank PS[2:0] select a pattern from Pattern Bank 1 BERTC0 BERT Control Register 0 70h 5 4 RINV PS2 IEOF n/a RPL3 (ANSI T1.403-1999 Annex (ITU O.153 (ITU O.151 (non-QRSS (ITU O.151 133 PS1 PS0 RPL2 RPL1 DS3112 0 RESYNC 0 8 RPL0 0 ...
Page 81
... BERT either goes into or out of synchronization) ( Figure 8 interrupt masked 1 = interrupt enabled Length Code Length 18 Bits 0001 19 Bits 22 Bits 0101 23 Bits 26 Bits 1001 27 Bits 30 Bits 1101 31 Bits Figure 8 133 Code Length Code 0010 20 Bits 0011 0110 24 Bits 0111 1010 28 Bits 1011 1101 32 Bits 1111 DS3112 ...
Page 82
... ERROR RATE INSERTED No errors automatically inserted - error per 10 bits error per 100 bits error per 1kbits error per 10kbits error per 100kbits error per 1Mbits error per 10Mbits) ALTERNATING COUNT ACTION 82 of 133 — — — AWC2 AWC1 DS3112 AWC0 0 ...
Page 83
... BERT Repetitive Pattern 0 (lower word) 74h 5 4 RP5 RP4 RP13 RP12 0 0 BERTRP1 BERT Repetitive Pattern 1 (upper word) 76h 5 4 RP21 RP20 RP29 RP28 133 RP3 RP2 RP1 RP11 RP10 RP9 RP19 RP18 RP17 RP27 RP26 RP25 DS3112 0 RP0 0 8 RP8 0 0 RP16 0 8 RP24 0 ...
Page 84
... BBC5 BBC4 BBC13 BBC12 BBC11 0 0 BERTBC1 BERT 32-Bit Bit Counter (upper word) 7Ah 5 4 BBC21 BBC20 BBC19 BBC29 BBC28 BBC27 133 BBC3 BBC2 BBC1 BBC10 BBC9 BBC18 BBC17 BBC26 BBC25 DS3112 0 BBC0 0 8 BBC8 0 0 BBC16 0 8 BBC24 0 ...
Page 85
... Bits 8 to 15: BERT 24-Bit Error Counter (BEC0 to BEC7). Lower byte of the 24-bit counter. See the BERTEC1 register description for details. BERTEC0 BERT 24-Bit Error Counter (lower) and Status Information 7Ch 5 4 RA0 RLOS — — BEC5 BEC4 0 0 8-1 133 BED BBCO BECO — — — BEC3 BEC2 BEC1 (Figure DS3112 0 SYNC — 8 BEC0 0 8-1). ...
Page 86
... Bits 1 & 2) Mask IEOF (BERTC0 Bit 13) BERTEC1 BERT 24-Bit Error Counter (upper) 7Eh 5 4 BEC13 BEC12 BEC11 BEC21 BEC20 BEC19 133 BERT OR Status Bit (MSR Bit 2) INT* Mask Hardware Signal BERT (IMSR Bit BEC10 BEC9 BEC18 BEC17 DS3112 0 BEC8 0 8 BEC16 0 ...
Page 87
... HDLC CONTROLLER The DS3112 contains an on-board HDLC controller with 256-byte buffers in both the transmit and receive paths. When the device is operated in the T3 mode, the HDLC controller is only active in the C- Bit Parity mode. When the device is operated in the E3 mode, the user has the option to connect the HDLC controller to the Sn bit position ...
Page 88
... Bit 4: Transmit Flag/Idle Select (TFS). This control bit determines whether flags or idle bytes will be transmitted in between packets 7Eh (flags FFh (idle) HCR HDLC Control Register 80h 5 4 THR TFS — — RHWMS0 TLWMS2 TLWMS1 133 TCRCI TZSD — TLWMS0 RID DS3112 0 TCRCD 0 8 TID 0 ...
Page 89
... FIFO contains more than the number of bytes configured by these bits, the RHWM status bit will be set to a one. RHWMS2 RHWMS1 RHWMS0 TRANSMIT LOW WATERMARK (bytes 112 0 144 1 176 0 208 1 240 RECEIVE HIGH WATERMARK (bytes 112 0 144 1 176 0 208 1 240 89 of 133 DS3112 ...
Page 90
... REASON FOR INVALID RECEPTION OF THE PACKET — Corrupt CRC Incoming packet was either too short (three or fewer bytes including the CRC) or did not contain an integral number of octets Abort sequence detected 90 of 133 — — — PS1 PS0 CBYTE — — — DS3112 0 D0 — 8 OBYTE — ...
Page 91
... HSR HDLC Status Register 86h 5 4 RPS RHWM — — ROVR TEMPTY — — 133 — — — — — — — TLWM — — — — TFL3 TFL2 TFL1 — — — DS3112 TMEND 0 0 TEND — 8 TFL0 — ...
Page 92
... DS3112 ...
Page 93
... The setting of this bit can cause a hardware interrupt to occur if the RABT bit in the Interrupt Mask for HSR (IHSR) register is set to a one and the HDLC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read 133 DS3112 ...
Page 94
... Bit 6) Mask RPE (IHSR Bit 6) TUDR (HSR Bit 7) Mask TUDR (IHSR Bit 7) ROVR (HSR Bit 13) Mask ROVR (IHSR Bit 13) RABT (HSR Bit 15) Mask RABT (IHSR Bit 15 133 DS3112 HDLC Status Bit (MSR Bit 3) INT* Mask Hardware Signal HDLC (IMSR Bit 3) ...
Page 95
... Bit 15: Receive Abort Sequence Detected (RABT interrupt masked 1 = interrupt unmasked IHSR Interrupt Mask for HDLC Status Register 88h 5 4 RPS RHWM ROVR — 0 — 133 — TLWM — — 0 — — — — — — — DS3112 0 TEND 0 8 — — ...
Page 96
... Receive FEAC FIFO Overflow (RFFO) status bit will be set. The DS3112 can transmit two different FEAC codewords. This is useful if the host wishes to generate a Loopback Command which is made FEAC codewords that indicate the type of loopback followed by 10 FEAC codewords that indicate which line looped back ...
Page 97
... Receive FEAC Idle (RFI) bit in the FSR register interrupt masked 1 = interrupt unmasked Bit 15: Receive FEAC Controller Reset (RFR). A zero to one transition will reset the receive FEAC controller and flush the Receive FEAC FIFO. This bit must be cleared and set again for a subsequent reset. ACTION 97 of 133 DS3112 ...
Page 98
... Receive FEAC FIFO has been read and then fills beyond capacity). FSR FEAC Status Register 92h 5 4 — — — — RFF5 RFF4 RFF3 — — 133 — — RFI — — — RFF2 RFF1 — — — DS3112 0 RFCD — 8 RFF0 — ...
Page 99
... The DS3112 device supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, IDCODE DS3112 contains the following items that meet the requirements set by the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture: ...
Page 100
... The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. Figure 11-2. TAP Controller State Machine Test-Logic-Reset 1 0 Run-Test/Idle 0 1 Select 1 DR-Scan 0 1 Capture-DR 0 Shift- Exit1 Pause- Exit2-DR 1 Update- 100 of 133 DS3112 Figure 11-2 1 Select IR-Scan 0 1 Capture-IR 0 Shift- Exit1-IR 0 Pause- Exit2-IR 1 Update- ...
Page 101
... Test-Logic-Reset Upon power-up of the DS3112, the TAP controller will be in the Test-Logic-Reset state. The Instruction register will contain the IDCODE instruction. All system logic on the DS3112 will operate normally. 11.1.2 Run-Test-Idle Run-Test-Idle is used between scan operations or during specific tests. The Instruction register and Test register will remain idle ...
Page 102
... JTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising edge on JTCLK with JTMS low will put the controller in the Run-Test-Idle state. With JTMS high, the controller will enter the Select-DR-Scan state. 102 of 133 DS3112 ...
Page 103
... The device ID code will always have a one in the LSB position. The next 11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version. The device ID code for the DS3112 is 0000B143h. 11.2.5 HIGHZ All digital outputs will be placed into a high impedance state ...
Page 104
... Test Registers IEEE 1149.1 requires a minimum of two test registers, the bypass register and the boundary scan register. An optional test register, the Identification register, has been included in the DS3112 design used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller. ...
Page 105
... LTCLK23 P19 57 LTDAT23 P18 58 LRCLK23 R20 59 LRDAT23 R19 60 LTCLK22 P17 61 LTDAT22 R18 62 LRCLK22 T20 63 LRDAT22 T19 64 LTCLK21 T18 65 LTDAT21 U20 66 LRCLK21 V20 67 LRDAT21 T17 68 LTCLK20 U18 69 LTDAT20 U19 I/O OR CONTROL BIT DESCRIPTION FTSOF is an input 0 = FTSOF is an output 105 of 133 DS3112 ...
Page 106
... V10 103 LRDAT12 W10 104 LTCLK11 Y9 105 LTDAT11 W9 106 LRCLK11 V9 107 LRDAT11 U9 108 LTCLK10 Y8 109 LTDAT10 W8 110 LRCLK10 V8 111 LRDAT10 Y7 112 LTCLK9 W7 113 LTDAT9 V7 114 LRCLK9 Y6 115 LRDAT9 W6 116 LTCLK8 U7 117 LTDAT8 V6 118 LRCLK8 Y5 I/O OR CONTROL BIT DESCRIPTION 106 of 133 DS3112 ...
Page 107
... LRDATB L3 152 LTCLKA L2 153 LTDATA L1 154 LRCLKA K1 155 LRDATA K3 156 CA7 K2 157 CA6 J1 158 CA5 J2 159 CA4 J3 160 CA3 J4 161 CA2 H1 162 CA1 H2 163 CA0 H3 164 CD15_OUT G1 165 CD15_IN G1 166 CD14_OUT G2 167 CD14_IN G2 I/O OR CONTROL BIT DESCRIPTION 107 of 133 DS3112 ...
Page 108
... CD6_OUT E3 183 CD6_IN E3 184 CD5_OUT D1 185 CD5_IN D1 186 CD4_OUT C1 187 CD4_IN C1 188 CD3_OUT E4 189 CD3_IN E4 190 CD2_OUT D3 191 CD2_IN D3 192 CD1_OUT D2 193 CD1_IN D2 194 CD0_OUT C2 195 CD0_IN C2 196 CD_ENB_N Control bit I/O OR CONTROL BIT DESCRIPTION input output 108 of 133 DS3112 ...
Page 109
... This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability. Table 1 -1. Recommended DC Operating Conditions 0°C to +70°C for DS3112 PARAMETER Logic 1 Logic 0 Supply Table 1 -2 ...
Page 110
... AC ELECTRICAL CHARACTERISTICS Table 1 -1. AC Characteristics—Low-Speed (T1 and E1) Ports 3 = 3.3V ±5 0°C to +70°C for DS3112 (See Figure 13- 1.) PARAMETER LRCLK/LRCCLK/LTCLK/LTCCLK Clock Period LRCLK Clock High Time LTCLK/LTCCLK/LRCCLK Clock High Time LRCLK Clock Low Time LTCLK/LTCCLK/LRCCLK Clock Low Time LTDAT Setup Time to the Falling ...
Page 111
... Figure 13-1. Low-Speed (T1 and E1) Port AC Timing Diagram LRCLK (or LRCCLK) / LTCLK (or LTCCLK) Normal Mode LRCLK (or LRCCLK) / LTCLK (or LTCCLK) Inverted Mode LTDAT LRDAT 111 of 133 t3 ls_ac DS3112 ...
Page 112
... Table 13-2. AC Characteristics—High-Speed (T3 and E3) Ports = 3.3V ±5 0°C to +70°C for DS3112 (See Figure 13- 2.) PARAMETER HRCLK/HTCLK Clock Period HRCLK Clock Low Time HRCLK Clock High Time HRPOS/HRNEG Setup Time to the Rising Edge or Falling Edge of HRCLK HRPOS/HRNEG Hold Time from the ...
Page 113
... Table 13-3. AC Characteristics–Framer (T3 and E3) Ports = 3.3V ±5 0°C to +70°C for DS3112 (See Figure 13- 3.) PARAMETER FRCLK/FTCLK Clock Period FTCLK Clock Low Time FTCLK Clock High Time FTD/FTSOF Setup Time to the Rising Edge or Falling Edge of FTCLK FTD/FTSOF Hold Time from the ...
Page 114
... Table 13-4. AC Characteristics—CPU Bus (Multiplexed and Nonmultiplexed) = 3.3V ±5 0°C to +70°C for DS3112 (See Figure 13- 4, Figure 13-5, and Figure 13-11.) PARAMETER Setup Time for CA[7:0] Valid to CCS Active Setup Time for CCS Active to CRD, CWR, or CDS Active Delay Time from CRD or CDS Active ...
Page 115
... Figure 13-4. Intel Read Cycle (Nonmultiplexed) CA[7:0] CD[15:0] CWR CCS CRD Figure 13-5. Intel Write Cycle (Nonmultiplexed) CA[7:0] CD[15:0] CRD CCS CWR Address Valid Data Valid Address Valid 115 of 133 t10 t10 DS3112 ...
Page 116
... Figure 13-6. Motorola Read Cycle (Nonmultiplexed) CA[7:0] CD[15:0] CR/W t1 CCS CDS Figure 13-7. Motorola Write Cycle (Nonmultiplexed) CA[7:0] CD[15:0] CR/W CCS CDS Address Valid Data Valid t2 t3 Address Valid 116 of 133 DS3112 t10 t10 ...
Page 117
... Figure 13-9. Intel Write Cycle (Multiplexed) t13 CALE t11 Address CA[7:0] Valid t14 t14 CD[15:0] CRD CCS CWR NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF CALE OR A VALID ADDRESS, WHICHEVER OCCURS FIRST. t12 Data Valid t12 117 of 133 t5 t4 t10 t10 DS3112 ...
Page 118
... Figure 13-11. Motorola Write Cycle (Multiplexed) t13 CALE t11 Address CA[7:0] Valid t14 t14 CD[15:0] CR/W CCS CDS NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF CALE OR A VALID ADDRESS, WHICHEVER OCCURS FIRST. t12 Data Valid t12 118 of 133 DS3112 t5 t4 t10 t10 ...
Page 119
... Table 1 -5. AC Characteristics—JTAG Test Port Interface 3 = 3.3V ±5 0°C to +70°C for DS3112 (See Figure 13-1 2.) PARAMETER JTCLK Clock Period JTCLK Clock Low Time JTCLK Clock High Time JTMS/JTDI Setup Time to the Rising Edge of JTCLK JTMS/JTDI Hold Time from the ...
Page 120
... Table 13-6. AC Characteristics—Reset and Manual Error Counter/Insert Signals = 3.3V ±5 0°C to +70°C for DS3112 (See Figure 13 PARAMETER RST Low Time FRMECU/FTMEI High Time FRMECU/FTMEI Low Time Figure 13-13. Reset and Manual Error Counter/Insert AC Timing Diagram RST t2 FRMECU/ FTMEI = -40°C to +85°C for DS3112N.) ...
Page 121
... DS3134 HDLC controller. Figure 14-2 shows an example of a dual unchannelized T3/E3 application. In this application, the multiplexing capability of the DS3112 is disabled and it is only used as a T3/E3 framer. Figure 14-1. Channelized T3/E3 Application 8.192MHz ...
Page 122
... Framer & M13/ E13/ G747 Mux 122 of 133 DS3150 T3/E3 bipolar Line I/F T3/E3 Line Interface - or - Optical OC-3/ NRZ I/F I/F OC-12/ OC-48 Mux DS3150 T3/E3 bipolar Line I/F T3/E3 Line Interface - or - Optical OC-3/ NRZ I/F I/F OC-12/ OC-48 Mux DS3112 ...
Page 123
... F2 overhead bit in the last block would be a stuff bit instead of an information bit. Figure 14-3 ). The four M subframes are transmitted one after 14-3. DESCRIPTION Figure 14-3 123 of 133 Table 14-2 and the placements of the ). In each stuff block there is an Figure 14-4 the position DS3112 ...
Page 124
... Info Info Info Bit 3 Bit 4 Bit 5 Bit 6 Stuff Info Info Info Bit 3 Bit 4 Bit 5 Bit 6 Info Stuff Info Info Bit 3 Bit 4 Bit 5 Bit 6 124 of 133 DS3112 Stuff Block Info F2 Info Bits (1) Bits Stuff Block Info F2 Info Bits (1) Bits Stuff Block 48 48 ...
Page 125
... F4 overhead bit in the last block would be a stuff bit instead of an information bit. Figure 14-5 shows the placements of the overhead bits. DESCRIPTION Figure 14-5 125 of 133 DS3112 Table 14-3 shows the Table 14- each stuff block there is an ...
Page 126
... Must be set to 1. Must be set to 1. Must be set to 1. Must be set to 1. Must be set to 1. Must be set to 1. 126 of 133 DS3112 Table 14-4 DESCRIPTION ...
Page 127
... Info C3 Info F4 (0) Bits Bits (1) Stuff Block Info C3 Info F4 (0) Bits Bits (1) Stuff Block Info C3 Info F4 (0) Bits Bits (1) Stuff Block Info C3 Info F4 (0) Bits Bits (1) DS3112 84 Info Bits 84 Info Bits 84 Info Bits 84 Info Bits 84 Info Bits 84 Info Bits 84 Info Bits ...
Page 128
... Bit 7 Bit 8 Info Info Info ...... Bit 6 Bit 7 Bit 8 Info Info Info ...... Bit 6 Bit 7 Bit 8 Stuff Info Info ...... Bit 6 Bit 7 Bit 8 Info Stuff Info ...... Bit 6 Bit 7 Bit 8 DS3112 Info Bit 84 Info Bit 84 Info Bit 84 Info Bit 84 Info Bit 84 Info Bit 84 Info Bit 84 ...
Page 129
... Stuffing Bit position will be used for tributary data. When the Justification Control Bits are majority decoded to be one, the Stuffing Bit will not be used for tributary data. Figure 14-7 ). The four sets are transmitted one 129 of 133 DS3112 Figure 14-8 ). ...
Page 130
... I = CONTROL STUFFING BIT NUMBER J = TRIBUTARY NUMBER 130 of 133 b ...bits from the tributaries... 41 12 ...bits from the tributaries... b b ...bits from the tributaries... 41 12 ...bits from the tributaries... DS3112 Bit 212 Bit 212 Bit 212 Bit 212 Bit 384 Bit 384 Bit 384 Bit 384 ...
Page 131
... T1 lines. We will only discuss the G.747 multiplexing scheme in this section. See Section 14.6 for details on the multiplexing scheme (e.g., M23) and the T3 framing structure. Table 14-6. G.747 Carrier Rates NOMINAL DATA CARRIER RATE (Mbps) LEVEL 2.048 6.312 44.736 131 of 133 DS3112 ...
Page 132
... J = TRIBUTARY NUMBER I = BIT NUMBER J = TRIBUTARY NUMBER I = CONTROL STUFFING BIT NUMBER J = TRIBUTARY NUMBER 132 of 133 14-9). The five sets are transmitted one b ...bits from the tributaries... 32 13 ...bits from the tributaries... DS3112 Bit 168 Bit 168 Bit 168 Bit 168 Bit 168 ...
Page 133
... No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. 133 of 133 © 2006 Maxim Integrated Products DS3112 ...