DS3112+W Maxim Integrated Products, DS3112+W Datasheet - Page 78

• Manufacturer Part Number: DS3112+W
• Description: IC MUX T3/E3 3.3V 256-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3112+W

• Controller Type: Framer, Multiplexer
• Interface: Parallel/Serial
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8 BERT
The BERT block can generate and detect the following patterns:
The BERT receiver has a 32-bit bit counter and a 24-bit error counter. It can generate interrupts on
detecting a bit error, a change in synchronization, or if an overflow occurs in the bit and error counters.
See Section
block, the host must configure the BERT mux via the BERT mux control register (Section 8.1). Data can
be routed to the receive side of the BERT from either the T3/E3 framer or from one of the 28 T1 or 16/21
E1 receive ports. Data from the transmit side of the BERT can be inserted either into the T3/E3 framer or
into one of the 28 T1 or 16/21 E1 transmit ports. See
where data to and from the BERT can be placed.
8.1 BERT Register Description
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 4: Receive BERT Port Select Bits 0 to 4 (RBPS0 to RBPS4). These bits determine if data from any of
the 28 T1 or 16/21 E1 receive ports or the T3/E3 receive framer (with or without the overhead bits) will be routed
to the receive side of the BERT. If these bits are set to 11101, only the T3/E3 payload data will be routed to the
receive BERT. If these bits are set to 11110, all T3/E3 data (payload and the overhead bits) will be routed to the
receive BERT.
RBPS4:0
00000
00001
00010
00011
00100
00101
00110
00111
10000
10001
10010
10011
10100
10101
10110
10111
•
•
•
Pseudorandom patterns 2
A repetitive pattern from 1 to 32 bits in length
Alternating (16-bit) words that flip every 1 to 256 words
No Data
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 16
Port 17
Port 18
Port 19
Port 20
Port 21
Port 22
Port 23
8.1
—
—
15
—
—
7
for details on status bits and interrupts from the BERT block. To activate the BERT
—
—
14
—
—
6
11101
11110
11111
01000
01001
01010
01011
01100
01101
01110
01111
11000
11001
11010
11011
11100
BERTMC
BERT Mux Control Register
0x6Eh
7
- 1, 2
T3/E3 Framer (payload + overhead bits)
Illegal State
Port 8
Port 9
Port 10
Port 11
Port 12
Port 13
Port 14
Port 15
Port 24
Port 25
Port 26
Port 27
Port 28
T3/E3 Framer (payload bits only)
11
—
—
13
—
—
5
- 1, 2
15
RBPS4
TBPS4
78 of 133
- 1, and QRSS
12
4
0
0
Figure 1-1
RBPS3
TBPS3
11
3
0
0
and
Figure 1-2
RBPS2
TBPS2
10
2
0
0
for a visual description of
RBPS1
TBPS1
1
0
9
0
RBPS0
TBPS0
DS3112
0
0
8
0