DS3112+W Maxim Integrated Products, DS3112+W Datasheet - Page 85

• Manufacturer Part Number: DS3112+W
• Description: IC MUX T3/E3 3.3V 256-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3112+W

• Controller Type: Framer, Multiplexer
• Interface: Parallel/Serial
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: Real-Time Synchronization Status (SYNC). Read-only real-time status of the synchronizer (this bit is not
latched). Will be set when the incoming pattern matches for 32 consecutive bit positions. Will be cleared when six
or more bits out of 64 are received in error.
Bit 1: BERT Error Counter Overflow (BECO). A latched read-only event-status bit that is set when the 24-bit
BERT Error Counter (BEC) saturates. Cleared when read and will not be set again until another overflow occurs
(i.e., the BEC counter must be cleared and allowed to overflow again). The setting of this status bit can cause a
hardware interrupt to occur if the IEOF bit in BERT Control Register 0 is set to a one and the BERT bit in the
Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read
(Figure
Bit 2: BERT Bit Counter Overflow (BBCO). A latched read-only event-status bit that is set when the 32-bit
BERT Bit Counter (BBC) saturates. Cleared when read and will not be set again until another overflow occurs (i.e.,
the BBC counter must be cleared and allowed to overflow again). The setting of this status bit can cause a
hardware interrupt to occur if the IEOF bit in BERT Control Register 0 is set to a one and the BERT bit in the
Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read
(Figure
Bit 3: Bit Error Detected (BED). A latched read-only event status bit that is set when a bit error is detected. The
receive BERT must be in synchronization for it to detect bit errors. This bit will be cleared when read. The setting
of this status bit can cause a hardware interrupt to occur if the IEBED bit in BERT Control Register 0 is set to a one
and the BERT bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to
clear when this bit is read
Bit 4: Receive Loss Of Synchronization (RLOS). A latched read-only alarm-status bit that is set whenever the
receive BERT begins searching for a pattern. Once synchronization is achieved, this bit will remain set until read.
A change in this status bit (i.e., the synchronizer goes into or out of synchronization) can cause a hardware interrupt
to occur if the IESYNC bit in BERT Control Register 0 is set to a one and the BERT bit in the Interrupt Mask for
MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read
Bit 5: Receive All Zeros (RA0). A latched read-only alarm-status bit that is set when 31 consecutive zeros are
received. Allowed to be cleared once a one is received.
Bit 6: Receive All Ones (RA1). A latched read-only alarm-status bit that is set when 31 consecutive ones are
received. Allowed to be cleared once a zero is received.
Bits 8 to 15: BERT 24-Bit Error Counter (BEC0 to BEC7). Lower byte of the 24-bit counter. See the
BERTEC1 register description for details.
8-1).
8-1).
BEC7
—
—
15
7
0
(Figure
BEC6
RA1
—
14
6
0
8-1).
BERTEC0
BERT 24-Bit Error Counter (lower) and Status Information
7Ch
BEC5
RA0
—
13
5
0
85 of 133
RLOS
BEC4
—
12
4
0
BEC3
BED
—
11
3
0
BBCO
BEC2
—
10
2
0
BECO
BEC1
—
1
9
0
(Figure
8-1).
SYNC
BEC0
—
DS3112
0
8
0