DS3112+W Maxim Integrated Products, DS3112+W Datasheet - Page 22
![IC MUX T3/E3 3.3V 256-PBGA](/photos/6/82/68222/406-256-bga_sml.jpg)
DS3112+W
Manufacturer Part Number
DS3112+W
Description
IC MUX T3/E3 3.3V 256-PBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3112.pdf
(133 pages)
Specifications of DS3112+W
Controller Type
Framer, Multiplexer
Interface
Parallel/Serial
Voltage - Supply
3.135 V ~ 3.465 V
Current - Supply
150mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
256-PBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Signal Name:
Signal Description:
Signal Type:
This signal will be forced high when the receive T3/E3 framer is in a Loss Of Signal (LOS) state. It will
remain high as long as the LOS state persists and will return low when the framer exits the LOS state. See
Section
software bit in the T3/E3 Status Register (Section 5.3).
Signal Name:
Signal Description:
Signal Type:
This signal will be forced high when the receive T3/E3 framer is in a Loss Of Frame (LOF) state. It will
remain high as long as the LOF state persists and will return low when the framer synchronizes. See
Section
software bit in the T3/E3 Status Register (Section 5.3).
Figure 2-1. T3/E3 Receive Framer Timing
FRCLK
Inverted Mode
FRCLK
Normal Mode
FRD
(see note)
FRDEN
Data Enable Mode for T3
(see note)
FRDEN
Data Enable Mode for E3
(see note)
FRDEN
Gapped Clock Mode for T3
(see note)
FRDEN
Gapped Clock Mode for E3
(see note)
FRSOF
(see note)
5.3
5.3
for details on the set and clear criteria for this signal. LOS status is also available via a
for details on the set and clear criteria for this signal. LOF status is also available via a
FRLOS
T3/E3 Receive Framer Loss Of Signal
Output
FRLOF
T3/E3 Receive Framer Loss Of Frame
Output
NOTE: FRD, FRDEN, AND FRSOF CAN BE INVERTED VIA MASTER CONTROL REGISTER 3.
22 of 133
Last Bit of
the Frame
T3: X1
E3: Bit 1 of FAS
DS3112
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