DS3112+W Maxim Integrated Products, DS3112+W Datasheet - Page 5

• Manufacturer Part Number: DS3112+W
• Description: IC MUX T3/E3 3.3V 256-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3112+W

• Controller Type: Framer, Multiplexer
• Interface: Parallel/Serial
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS3112
LIST OF FIGURES
Figure 1-1. DS3112 Framer and Multiplexer Block Diagram (T3 Mode) ................................................................... 11
Figure 1-2. DS3112 Framer and Multiplexer Block Diagram (E3 Mode)................................................................... 12
Figure 1-3. DS3112 Framer and Multiplexer Block Diagram (G.747 Mode) ............................................................. 13
Figure 2-1. T3/E3 Receive Framer Timing ................................................................................................................ 22
Figure 2-2. T3/E3 Transmit Formatter Timing ........................................................................................................... 24
Figure 4-1. Event Status Bit....................................................................................................................................... 38
Figure 4-2. Alarm Status Bit....................................................................................................................................... 38
Figure 4-3. Real-Time Status Bit ............................................................................................................................... 39
Figure 4-4. BERT Status Bit Flow.............................................................................................................................. 41
Figure 4-5. HDLC Status Bit Flow.............................................................................................................................. 42
Figure 4-6. T2E2SR1 Status Bit Flow........................................................................................................................ 43
Figure 4-7. T2E2SR2 Status Bit Flow........................................................................................................................ 44
Figure 4-8. T1LB Status Bit Flow............................................................................................................................... 44
Figure 4-9. T3E3SR Status Bit Flow.......................................................................................................................... 45
Figure 5-1. T3E3SR Status Bit Flow.......................................................................................................................... 54
Figure 6-1. T2E2SR1 Status Bit Flow........................................................................................................................ 65
Figure 6-2. T2E2SR2 Status Bit Flow........................................................................................................................ 66
Figure 7-1. T1LBSR1 and T1LBSR2 Status Bit Flow ................................................................................................ 76
Figure 8-1. BERT Status Bit Flow.............................................................................................................................. 86
Figure 9-1. HSR Status Bit Flow................................................................................................................................ 94
Figure 11-1. JTAG Block Diagram............................................................................................................................. 99
Figure 11-2. TAP Controller State Machine............................................................................................................. 100
Figure 13-1. Low-Speed (T1 and E1) Port AC Timing Diagram.............................................................................. 111
Figure 13-2. High-Speed (T3 and E3) Port AC Timing Diagram ............................................................................. 112
Figure 13-3. Framer (T3 and E3) Port AC Timing Diagram..................................................................................... 113
Figure 13-4. Intel Read Cycle (Nonmultiplexed)...................................................................................................... 115
Figure 13-5. Intel Write Cycle (Nonmultiplexed)...................................................................................................... 115
Figure 13-6. Motorola Read Cycle (Nonmultiplexed) .............................................................................................. 116
Figure 13-7. Motorola Write Cycle (Nonmultiplexed)............................................................................................... 116
Figure 13-8. Intel Read Cycle (Multiplexed) ............................................................................................................ 117
Figure 13-9. Intel Write Cycle (Multiplexed) ............................................................................................................ 117
Figure 13-10. Motorola Read Cycle (Multiplexed) ................................................................................................... 118
Figure 13-11. Motorola Write Cycle (Multiplexed) ................................................................................................... 118
Figure 13-12. JTAG Test Port Interface AC Timing Diagram .................................................................................. 119
Figure 13-13. Reset and Manual Error Counter/Insert AC Timing Diagram............................................................ 120
Figure 14-1. Channelized T3/E3 Application ........................................................................................................... 121
Figure 14-2. Unchannelized Dual T3/E3 Application............................................................................................... 122
Figure 14-3. T2 M-Frame Structure ......................................................................................................................... 124
Figure 14-4. T2 Stuff Block Structure ...................................................................................................................... 124
Figure 14-5. T3 M-Frame Structure ......................................................................................................................... 127
Figure 14-6. T3 Stuff Block Structure ...................................................................................................................... 128
Figure 14-7. E2 Frame Structure ............................................................................................................................. 130
Figure 14-8. E3 Frame Structure ............................................................................................................................. 130
Figure 14-9. G.747 Frame Structure........................................................................................................................ 132
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