DS3112+W Maxim Integrated Products, DS3112+W Datasheet - Page 64

• Manufacturer Part Number: DS3112+W
• Description: IC MUX T3/E3 3.3V 256-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3112+W

• Controller Type: Framer, Multiplexer
• Interface: Parallel/Serial
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.3 T2/E2/G.747 Framer Status and Interrupt Register Description
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: See
other bits are read-write.
Bits 0 to 6: Loss Of Frame Occurrence (LOFn when n = 1 to 7). This latched read-only alarm-status bit will be
set to a one each time the corresponding T2/E2/G.747 framer detects a Loss Of Frame (LOF). This bit will be
cleared when read unless a LOF condition still exists in that T2/E2/G.747 framer. A change in state of the LOF in
one or more of the T2/E2/G.747 framers can cause the T2E2SR1 status bit (in the MSR register) to be set and a
hardware interrupt to occur if the IELOF bit is set to a one and the T2E2SR1 bit in the Interrupt Mask for MSR
(IMSR) register is set to a one
alarm criteria are described in
meaningless and should be ignored.
Bit 7: Interrupt Enable for Loss of Frame Occurrence (IELOF). This bit should be set to one if the host wishes
to have T2/E2/G.747 LOF occurrences cause a hardware interrupt or the setting of the T2E2SR1 status bit in the
MSR register
also be set to one for an interrupt to occur.
Bits 8 to 14: Alarm Indication Signal Detected (AISn when n = 1 to 7). This latched read-only alarm-status bit
will be set to a one each time the corresponding T2/E2/G.747 framer detects an incoming AIS alarm. This bit will
be cleared when read unless the AIS alarm still exists in that T2/E2/G.747 framer. A change in state of the AIS
detector in one or more of the T2/E2/G.747 framers can cause the T2E2SR1 status bit (in the MSR register) to be
set and a hardware interrupt to occur if the IEAIS bit is set to a one and the T2E2SR1 bit in the Interrupt Mask for
MSR (IMSR) register is set to a one
AIS alarm criteria is described in
are meaningless and should be ignored.
Bit 15: Interrupt Enable for Alarm Indication Signal (IEAIS). This bit should be set to one if the host wishes to
have T2/E2/G.747 AIS detection occurrences cause a hardware interrupt or the setting of the T2E2SR1 status bit in
the MSR register
also be set to one for an interrupt to occur.
0 = interrupt masked
1 = interrupt unmasked
0 = interrupt masked
1 = interrupt unmasked
Figure 6-1
IELOF
(Figure
IEAIS
15
7
0
0
(Figure
for details on the signal flow for the status bits in the T2E2SR1 register. Bits that are underlined are read-only; all
6-1). The T2E2SR1 bit in the Interrupt Mask for the Master Status Register (IMSR) must
6-1). The T2E2SR1 bit in the Interrupt Mask for the Master Status Register (IMSR) must
LOF7
AIS7
14
6
-
-
Table
(Figure
T2E2SR1
T2/E2 Status Register 1
34h
Table
6-1,
(Figure
6-1). The interrupt will be allowed to clear when this bit is read. The LOF
LOF6
6-1,
AIS6
Table
13
5
-
-
Table
6-1). The interrupt will be allowed to clear when this bit is read. The
6-2, and
6-2, and
64 of 133
LOF5
AIS5
12
4
-
-
Table
Table
6-3. In the E3 mode, LOF5 to LOF7 (bits 4 to 6) are
LOF4
AIS4
6-3. In the E3 mode, AIS5 to AIS7 (bits 4 to 6)
11
3
-
-
LOF3
AIS3
10
2
-
-
LOF2
AIS2
1
9
-
-
LOF1
AIS1
0
8
-
-
DS3112