DS3112+W Maxim Integrated Products, DS3112+W Datasheet - Page 68

• Manufacturer Part Number: DS3112+W
• Description: IC MUX T3/E3 3.3V 256-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3112+W

• Controller Type: Framer, Multiplexer
• Interface: Parallel/Serial
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.4 T1/E1 AIS Generation Control Register Description
Via the T1/E1 Alarm Indication Signal (AIS) Control Registers, the host can configure the DS3112 to
generate an unframed all ones signal in either the transmit or receive paths on the 28 T1 ports or the 16/21
E1 ports. On reset, the device will force AIS in both the transmit and receive paths and it is up to the host
to modify the T1/E1 AIS Generation Control Registers to allow normal T1/E1 traffic to traverse the
DS3112. See the block diagrams in Section
flow. When the M13/E13 multiplexer function is disabled in the DS3112 (see the UNCHEN control bit in
the Master Control Register 1 in Section
meaningless and can be set to any value.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15: Receive AIS Generation Control for T1/E1 Ports 1 to 16 (AIS1 to AIS2). These bits determine
whether the device will replace the demultiplexed T1/E1 data stream with an unframed all ones AIS signal. AIS1
controls the data at LRDAT1, AIS2 controls the data at LRDAT2, and so on. Since ports 4, 8, 12, 16, 20, 24, and
28 are not active in the G.747 mode, the AIS4, AIS8, AIS12, and AIS16 bits have no affect in the G.747 mode.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 11:Receive AIS Generation Control for T1 Ports 17 to 28 (AIS17 to AIS28). These bits determine
whether the device will replace the demultiplexed T1/E1 data stream with an unframed all ones AIS signal. AIS17
controls the data at LRDAT17, AIS18 controls the data at LRDAT18, and so on. Since ports 17 to 28 are not active
in the E3 mode, these bits have no effect in the E3 mode. Since ports 4, 8, 12, 16, 20, 24, and 28 are not active in
the G.747 mode, the AIS20, AIS24 and AIS28 bits have no affect in the G.747 Mode.
0 = send AIS to the LRDAT output
1 = send normal data to the LRDAT output
0 = send AIS to the LRDAT output
1 = send normal data to the LRDAT output
AIS16
AIS24
AIS8
15
15
—
—
7
0
0
7
0
AIS15
AIS23
AIS7
14
14
—
—
6
0
0
6
0
T1E1RAIS1
T1/E1 Receive Path AIS Generation Control Register 1
40h
T1E1RAIS2
T1/E1 Receive Path AIS Generation Control Register 2
42h
AIS14
AIS22
AIS6
13
13
—
—
5
5
0
0
0
4.2
1
for details), the T1/E1 AIS Generation Control Registers are
for details on where the AIS signal is injected into the data
68 of 133
AIS13
AIS21
AIS5
12
12
—
—
4
0
0
4
0
AIS12
AIS20
AIS28
AIS4
11
11
3
3
0
0
0
0
AIS11
AIS19
AIS27
AIS3
10
10
2
0
0
2
0
0
AIS10
AIS18
AIS26
AIS2
1
9
1
9
0
0
0
0
AIS17
AIS25
AIS1
AIS9
DS3112
0
0
8
0
0
0
8
0