DS3112+W Maxim Integrated Products, DS3112+W Datasheet - Page 88

• Manufacturer Part Number: DS3112+W
• Description: IC MUX T3/E3 3.3V 256-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3112+W

• Controller Type: Framer, Multiplexer
• Interface: Parallel/Serial
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

then the transmit HDLC controller will send an abort of seven ones in a row (FEh) followed by a
continuous transmission of either 7Eh (flags) or FFh (idle) and the Transmit FIFO Underrun (TUDR)
status bit will be set. When the FIFO underruns, the transmit HDLC controller should be reset by the host.
The transmit HDLC has been designed to minimize its real-time host support requirements. The transmit
FIFO is 256 bytes, which is deep enough to store the three T3 packets (Path ID, Idle Signal ID, and Test
Signal ID) that need to be sent once a second. Hence in T3 applications, the host only needs to access the
transmit HDLC once a second to load up the three messages. Once the host has loaded an outgoing
packet, it can monitor the Transmit Packet End (TEND) status bit to know when the packet has finished
being transmitted. Also, the host can be notified when the FIFO has emptied below a programmable level
called the low watermark. The host must never overfill the FIFO. To keep this from occurring, the host
can obtain the real-time depth of the transmit FIFO via the Transmit FIFO Level bits in the HDLC Status
Register (HSR).
9.2 HDLC Control and FIFO Register Description
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: Transmit CRC Defeat (TCRCD). When this bit is set low, the HDLC will automatically calculate and
append the 16-bit CRC to the outgoing HDLC message. When this bit is set high, the device will not append the
CRC to the outgoing message.
Bit 1: Transmit Zero Stuffer Defeat (TZSD). When this bit is set low, the HDLC will automatically enable the
zero stuffer in between the opening and closing flags of the HDLC message. When this bit is set high, the device
will not enable the zero stuffer under any condition.
Bit 2: Transmit CRC Invert (TCRCI). When this bit is set low, the HDLC will allow the CRC to be generated
normally. When this bit is set high, the device will invert all 16 bits of the generated CRC. This bit is ignored when
the CRC generation is disabled (TCRCD = 1). This bit is useful in testing HDLC operation.
Bit 4: Transmit Flag/Idle Select (TFS). This control bit determines whether flags or idle bytes will be transmitted
in between packets.
0 = enable CRC generation (normal operation)
1 = disable CRC generation
0 = enable zero stuffer (normal operation)
1 = disable zero stuffer
0 = do not invert the generated CRC (normal operation)
1 = Invert the generated CRC
0 = 7Eh (flags)
1 = FFh (idle)
RHWMS2
—
—
15
7
0
RHWMS1
RHR
14
6
0
0
HCR
HDLC Control Register
80h
RHWMS0
THR
13
5
0
0
TLWMS2
88 of 133
TFS
12
4
0
0
TLWMS1
—
—
11
3
0
TLWMS0
TCRCI
—
10
2
0
TZSD
RID
1
0
9
0
TCRCD
TID
DS3112
0
0
8
0