DS3112+W Maxim Integrated Products, DS3112+W Datasheet - Page 123

IC MUX T3/E3 3.3V 256-PBGA

DS3112+W

Manufacturer Part Number
DS3112+W
Description
IC MUX T3/E3 3.3V 256-PBGA
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS3112+W

Controller Type
Framer, Multiplexer
Interface
Parallel/Serial
Voltage - Supply
3.135 V ~ 3.465 V
Current - Supply
150mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
256-PBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
14.3
To understand the M12 function users must understand T2 framing. The T2 frame structure is made up of
four subframes called M subframes (
another (...M1/M2/M3/M4/M1/M2...) to make up the complete T2 M frame data structure. Each M
subframe is made up of six blocks and each block is made up of 49 bits. The first bit of each block is
dedicated to overhead and the next 48 bits are the information bits where the T1 data will be placed for
transport. The definitions of the overhead bits are shown in
overhead bits are shown in
Table 14-2. T2 Overhead Bit Assignments
14.4 M12 Multiplexing
The M12 function multiplexes four T1 lines into a single T2 line. Since there are four M subframes in the
T2 framing structure, it might be concluded that each M subframe supports one T1 line but this is not the
case. The four T1 lines are bit interleaved into the T2 framing structure. A bit from T1 line #1 is placed
immediately after the overhead bit, followed by a bit from T1 line #2, which is followed by a bit from T1
line #3, which is followed by a bit from T1 line #4, and then the process repeats. Since there are 48
information bits in each block, there are 12 bits from each T1 line in a block. The second and fourth T1
lines are logically inverted before the bit interleaving occurs.
The four T1 lines are mapped asynchronously into the T2 data stream. This implies that there is no T1
framing information passed to the T2 level. The four T1 lines can have independent timing sources and
they do not need to be timing locked to the T2 clock. To account for differences in timing, bit stuffing is
used. The last block of each M subframe is the stuff block (
associated stuff bit
be a zero) or a stuff bit (if the three C bits are decoded to be a one). As shown in
of the stuff bit varies depending on the M subframe. This is done to allow a stuffing opportunity to occur
on each T1 line in every T2 M frame. For example, if the C bits in M Subframe 2 were all set to one, then
the second bit after the F2 overhead bit in the last block would be a stuff bit instead of an information bit.
OVERHEAD BIT
(M1/M2/M3)
(C1/C2/C3)
T2 Framing Structure
(F1/F2)
M Bits
C Bits
F Bits
X Bit
(Figure
The M bits provide the frame alignment pattern for the four M subframes. Like all
framing patterns, the M bits are fixed to a certain state (M1 = 0/M2 = 1/M3 = 1).
The F bits provide the frame alignment pattern for the M frame. Like all framing
patterns, the F bits are fixed to a certain state (F1 = 0/F2 = 1).
In the M12 application, the C bits are used to indicate when stuffing occurs. If all three
C Bits within a subframe are set to 1, then stuffing has occurred in the stuff block of
that subframe. If all three C Bits are set to zero, then no stuffing has occurred. When
the three C bits are not equal, a majority vote is used to determine the true state. The
exception to this rule is when the C3 bit is the inverse of C1 and C2. When this occurs,
it indicates that the T1 signal should be looped back.
The X bit is used as a Remote Alarm Indication (RAI). It will be set to a zero (X = 0)
when the T2 framer cannot synchronize. It will be set to a one (X = 1) otherwise.
Figure
14-4) that will be either an information bit (if the three C bits are decoded to
14-3.
Figure 14-3
123 of 133
). The four M subframes are transmitted one after
DESCRIPTION
Figure 14-3
Table 14-2
). In each stuff block there is an
and the placements of the
Figure 14-4
the position
DS3112

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