DS3112+W Maxim Integrated Products, DS3112+W Datasheet - Page 75

• Manufacturer Part Number: DS3112+W
• Description: IC MUX T3/E3 3.3V 256-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3112+W

• Controller Type: Framer, Multiplexer
• Interface: Parallel/Serial
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.6 T1 Line Loopback Command Status Register Description
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: See
read-only; all other bits are read-write.
Bits 0 to 15: T1 Line Loopback Command Status for Ports 1 to 16 (LLB1 to LLB16). These read-only real-
time status bits will be set to a one when the corresponding T2 framer detects that the C3 bit is the inverse of the
C1 and C2 bits for 5 consecutive frames. These bits will be allowed to clear when the C3 bit is not the inverse of
the C1 and C2 bits for five consecutive frames. LLB1 corresponds to T1/E1 Port 1, LLB2 corresponds to T1/E1
Port 2, and so on. The setting of any of the bits in T1LBSR1 or T1LBSR2 can cause a hardware interrupt to occur
if the T1LB bit in the Interrupt Mask for MSR (IMSR) is set to a one. In the E3 and G.747 modes, these bits are
meaningless and should be ignored.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 11: T1 Line Loopback Command Status for Ports 17 to 28 (LLB17 to LLB28). These read-only real-
time status bits will be set to a one when the corresponding T2 framer detects that the C3 bit is the inverse of the
C1 and C2 bits for 5 consecutive frames. These bits will be allowed to clear when the C3 bit is not the inverse of
the C1 and C2 bits for five consecutive frames. LLB17 corresponds to T1/E1 Port 17, LLB18 corresponds to T1/E1
Port 18, and so on. The setting of any of the bits in T1LBSR1 or T1LBSR2 can cause a hardware interrupt to occur
if the T1LB bit in the Interrupt Mask for MSR (IMSR) is set to a one. In the E3 and G.747 Modes, these bits are
meaningless and should be ignored.
Figure 7-1
LLB16
LLB24
LLB8
—
15
—
—
15
—
—
7
7
for details on the signal flow for the status bits in the T1LBSR1 and T1LBSR2 registers. Bits that are underlined are
LLB15
LLB23
LLB7
—
14
—
—
14
—
—
6
6
T1LBSR2
T1 Line Loopback Command Status Register 2
5Eh
T1LBSR1
T1 Line Loopback Command Status Register 1
5Ch
LLB14
LLB22
LLB6
—
13
—
—
13
—
—
5
5
LLB13
LLB21
75 of 133
LLB5
—
12
—
—
12
—
—
4
4
LLB12
LLB20
LLB28
LLB4
—
11
—
—
11
—
3
3
LLB11
LLB19
LLB27
LLB3
—
10
—
—
10
—
2
2
LLB10
LLB18
LLB26
LLB2
—
—
—
—
1
9
1
9
LLB17
LLB25
LLB1
LLB9
—
—
—
—
DS3112
0
8
0
8