DS3112+W Maxim Integrated Products, DS3112+W Datasheet - Page 53

• Manufacturer Part Number: DS3112+W
• Description: IC MUX T3/E3 3.3V 256-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3112+W

• Controller Type: Framer, Multiplexer
• Interface: Parallel/Serial
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.5 T3/E3 Framer Status and Interrupt Register Description
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: See
others are read-write.
Bit 0: Loss Of Signal Occurrence (LOS). This latched read-only alarm-status bit will be set to a one when the T3
or E3 framer detects a loss of signal. This bit will be cleared when read unless a LOS condition still exists. A
change in state of the LOS can cause a hardware interrupt to occur if the LOS bit in the Interrupt Mask for T3E3SR
(IT3E3SR) register is set to a one and the T3E3SR bit in the Interrupt Mask for MSR (IMSR) register is set to a
one. The interrupt will be allowed to clear when this bit is read. The LOS alarm criteria are described in
and
Bit 1: Loss Of Frame Occurrence (LOF). This latched read-only alarm status bit will be set to a one when the T3
or E3 framer detects a loss of frame. This bit will be cleared when read unless a LOF condition still exists. A
change in state of the LOF can cause a hardware interrupt to occur if the LOF bit in the Interrupt Mask for T3E3SR
(IT3E3SR) register is set to a one and the T3E3SR bit in the Interrupt Mask for MSR (IMSR) register is set to a
one. The interrupt will be allowed to clear when this bit is read. The LOF alarm criteria are described in
and
Bit 2: Alarm Indication Signal Detected (AIS). This latched read-only alarm-status bit will be set to a one when
the T3 or E3 framer detects an incoming Alarm Indication Signal. This bit will be cleared when read unless an AIS
signal is still present. A change in state of the AIS detection can cause a hardware interrupt to occur if the AIS bit
in the Interrupt Mask for T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the Interrupt Mask for
MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read. The AIS alarm
detection criteria is described in
Bit 3: Remote Alarm Indication Detected (RAI). This latched read-only alarm status bit will be set to a one when
the T3 or E3 framer detects an incoming Remote Alarm Indication (RAI) signal. This bit will be cleared when read
unless an RAI signal is still present. A change in state of the RAI detection can cause a hardware interrupt to occur
if the RAI bit in the Interrupt Mask for T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the
Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read.
The RAI alarm detection criteria are described in
codes when the device is operated in the C-Bit Parity Mode.
Bit 4: T3 Idle Signal Detected (T3IDLE). This latched read-only alarm status bit will be set to a one when the T3
framer detects an incoming idle signal. This bit will be cleared when read unless the idle signal is still present. A
change in state of idle detection can cause a hardware interrupt to occur if the IDLE bit in the Interrupt Mask for
T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the Interrupt Mask for MSR (IMSR) register is
set to a one. The IDLE detection criteria are described in
bit is read. When the DS3112 is operated in the E3 mode, this status bit should be ignored.
Bit 5: Transmit T3/E3 Start Of Frame (TSOF). This latched read-only event-status bit will be set to a one on
each T3/E3 transmit frame boundary. This bit is a software version of the FTSOF hardware signal and it will be
cleared when read. The setting of this bit can cause a hardware interrupt to occur if the TSOF bit in the Interrupt
Table
Table
Figure 5-1
5-2.
5-2.
—
—
15
—
—
7
for details on the signal flow for the status bits in the T3E3SR register. Bits that are underlined are read-only. All
RSOF
—
14
—
—
6
Table 5-1
T3E3SR
T3/E3 Status Register
12h
TSOF
and
—
13
—
—
5
Table
Table 5-1
T3IDLE
5-2.
53 of 133
—
12
—
—
4
Table
and
5-1. The interrupt will be allowed to clear when this
Table
RAI
—
11
—
—
3
5-2. RAI can also be indicated via the FEAC
AIS
—
10
—
—
2
LOF
—
—
—
1
9
Table 5-1
Table 5-1
LOS
—
—
—
DS3112
0
8