DS3112+W Maxim Integrated Products, DS3112+W Datasheet - Page 41

• Manufacturer Part Number: DS3112+W
• Description: IC MUX T3/E3 3.3V 256-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3112+W

• Controller Type: Framer, Multiplexer
• Interface: Parallel/Serial
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

device detects a clock at FTCLK. The HRCLK checks for the presence of the FTCLK. On reset, both the LOTC
and LORC status bits will be set and then immediately cleared if the clock is present.
Bit 11: Loss Of Receive Clock Detected (LORC). This read-only real-time status bit will be set to a one when the
device detects that the HRCLK clock has not toggled for 200ns (±100ns). This bit will be cleared when a clock is
detected at the HRCLK input. The setting of this status bit can cause a hardware interrupt to occur if the LORC bit
in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when the
device detects a clock at HRCLK. The FTCLK checks for the presence of the HRCLK. On reset, both the LOTC
and LORC status bits will be set and then immediately cleared if the clock is present.
Bit 12: State of the T3E3MS Input Signal (T3E3MS). This read-only real-time status bit reflects the current state
of the external T3E3MS input signal. This status bit cannot generate an interrupt.
Bit 13: State of the G.747E Input Signal (G.747E). This read-only real-time status bit reflects the current state of
the external G.747E input signal. This status bit cannot generate an interrupt.
Figure 4-4. BERT Status Bit Flow
Internal RLOS
Signal from
BERT
Internal Bit
Error Detected
Signal from
BERT
Internal Counter
Overflow
Signal from
BERT
NOTE: ALL EVENT AND ALARM LATCHES ABOVE ARE CLEARED WHEN THE BERTEC0 REGISTER IS READ.
Change in State Detect
Alarm Latch
Event Latch
Event Latch
IESYNC (BERTC0 Bit 15)
IEBED (BERTC0 Bit 14)
RLOS
(BERTEC0
Bit 4)
BED
(BERTEC0
Bit 3)
BECO or BBCO
(BERTEC0
Bits 1 & 2)
IEOF (BERTC0 Bit 13)
Event Latch
41 of 133
Mask
Mask
Mask
OR
BERT
(IMSR Bit 2)
Mask
BERT
Status Bit
(MSR Bit 2)
INT*
Hardware
Signal
DS3112