EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 85

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

DS785UM1
[31:28]
Cond
0000
0001
0010
0011
0100
0101
0110
1000
1001
1010
1011
1100
1101
0111
1110
1111
Table 3-5
The remaining bits in the instruction formats are interpreted as follows:
Mnemonic
Extension
• opcode1: MaverickCrunch co-processor-defined opcode
• opcode2: MaverickCrunch co-processor defined opcode
• CRn: MaverickCrunch co-processor-defined register
• CRd: MaverickCrunch co-processor-defined register
• CRm: MaverickCrunch co-processor-defined register
• Rn: Specifies an ARM base address register. These bits are ignored by the
• Rd: Specifies a source or destination ARM register
• cp_num: Co-processor number
• P: Pre-indexing (P=1) or post-indexing (P=0) addressing. This bit is ignored by the
• U: Specifies whether the supplied 8-bit offset is added to a base register (U=1) or
• N: Specifies the width of a data type involved in a move operation. The MaverickCrunch
CS/HS
CC/LO
EQ
NE
VC
GE
NV
PL
VS
LS
GT
LE
AL
MI
LT
HI
MaverickCrunch co-processor.
MaverickCrunch co-processor.
subtracted from a base register (U=0). This bit is ignored by the MaverickCrunch co-
processor.
shows the condition codes, which are bits [31:28] for each instruction format.
Carry Set/Unsigned Higher or Same
Signed Greater Than or Equal
Carry Clear/Unsigned Lower
Signed Less Than or Equal
Unsigned Lower or Same
Always (unconditional)
Plus/Positive or Zero
Signed Greater Than
Signed Less Than
Unsigned Higher
Minus/Negative
No Overflow
Meaning
Not Equal
Overflow
Never
Equal
Table 3-5. Condition Code Definitions
Copyright 2007 Cirrus Logic
Z clear, and either N set and V set, or N clear and V clear (Z = 0, N = V)
Z set, or N set and V clear, or N clear and V set (Z = 1, N ! = V)
N set and V clear, or N clear and V set (N ! = V)
N set and V set, or N clear and V clear (N = V)
Status Flag State
C set and Z clear
C clear or Z set
Z clear
C clear
N clear
V clear
C set
N set
V set
Z set
MaverickCrunch Co-Processor
-
-
EP93xx User’s Guide
3-15
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