EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 552

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

14
UART1HDLCAddMtchVal
14-30
UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide
31
15
Address:
30
14
29
13
28
12
CRCZ:
RXE:
TXE:
TUS:
CRCE:
CRCS:
0x808C_0210 - Read/Write
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
CRC zero seed
0 - Seed CRC calculations with all ones; that is, 0xFFFF
for 16 bit words and 0xFFFF_FFFF for 32 bit words.
1 - Seed CRC calculations with all zeros.
Applies to both RX and TX.
HDLC Receive Enable.
0 - Disable HDLC RX. If UART is still enabled, UART may
still receive normally.
1 - Enable HDLC RX.
HDLC Transmit Enable.
0 - Disable HDLC TX. If UART is still enabled, UART may
still transmit normally.
1 - Enable HDLC TX.
Transmit FIFO Underrun Select
0 - TX FIFO underrun causes CRC (if enabled) and stop
flag to be transmitted.
1 - TX FIFO underrun causes abort (escape-flag) to be
transmitted.
CRC enable.
0 - No CRC is generated by TX or expected by RX.
1 - HDLC TX automatically generates and sends a CRC at
the end of a packet, and HDLC RX expects a CRC at the
end of a packet.
CRC size.
0 - CRC-CCITT (16 bits): x
1 - CRC-32: x
x
If inverted (see CRCN bit) the CRC-16 check value is
0x1D0F and the CRC-32 check value is 0xC704_DD7B.
Otherwise the check value is zero.
8
+ x
24
8
7
AMV
AMV
+ x
5
23
7
+ x
32
4
+ x
+ x
22
6
26
2
+ x + 1
+ x
21
5
23
16
+ x
+ x
20
4
22
12
+ x
+ x
19
3
16
5
+ x
+ 1
12
18
2
+ x
11
17
1
DS785UM1
+ x
10
16
0
+