EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 339
![IC ARM9 SOC PROCESSOR 208LQFP](/photos/12/23/122385/mfg_ep9302_parts_sml.jpg)
EP9302-CQZ
Manufacturer Part Number
EP9302-CQZ
Description
IC ARM9 SOC PROCESSOR 208LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9302-IQZ.pdf
(42 pages)
3.EP9302-IQZ.pdf
(4 pages)
4.EP9302-IQZ.pdf
(40 pages)
Specifications of EP9302-CQZ
Program Memory Type
ROMless
Package / Case
208-LQFP
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Data Ram Size
16 bit
Interface Type
USB, USART, SPI
Maximum Clock Frequency
200 MHz
Number Of Programmable I/os
37
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9302A-Z
Controller Family/series
(ARM9)
No. Of I/o's
19
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1132 - KIT DEVELOPMENT EP9302 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1137
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- EP9307-CRZ PDF datasheet
- EP9302-IQZ PDF datasheet #2
- EP9302-IQZ PDF datasheet #3
- EP9302-IQZ PDF datasheet #4
- Current page: 339 of 824
- Download datasheet (13Mb)
DS785UM1
9.2.4 Interrupts
9.2.4.1 Interrupt Processing
9.2.5 Initialization
Interrupts can be associated with on chip status or with off-chip status. (Off-chip status is
status that has been transferred to either the transmit or receive status queue.) The status for
any outstanding interrupt event is available via two different register addresses: IntStsP
(Interrupt Status Preserve) and IntStsC (Interrupt Status Clear).
Reading the IntStsP register has no effect on the bits set in the register. They may be
explicitly cleared by writing a “1” back to any of the bit positions. This allows the Host to
process interrupt events across multiple routines, only clearing the bits for which it has
processed the corresponding events.
The IntStsC register will clear the status for all outstanding events when it is read. This
provides a quick mechanism for the Host to accept all the outstanding events in one read and
not incur the additional IO cycles required in specifically clearing the events.
The following is the suggested hardware initialization sequence for a driver:
1. Determine what PHYs are available (poll PHYs via the management interface via
2. Enable auto negotiation to determine the mode of operation 10/100 Mbit, FDX/HDX.
3. Set RXDQBAdd and RXDCurAdd to point to the start of the receive descriptor queue
4. Set RXDQBLen to the length of the receive descriptor queue.
5. Set RXStsQBAdd and RXStsQCurAdd to point at the start of the receive status queue.
6. Set RXStsQBLen to the length of the status queue.
7. Set BMCtl.RxEn which clears the RXDEnq/RXStsEnq registers and initializes internal
8. Set TXDQBAdd and TXDQCurAdd to point to the start of the transmit descriptor queue.
9. Set TXDQBLen to the length of the transmit descriptor queue.
10.Set TXStsQBAdd and TXStsQCurAdd to point to the start of the transmit status queue.
11.Set TXStsQBLen to the length of the status queue.
12.Set BMCtl.TxEn which clears the TXDEnq and initializes internal pointers to the
13.Set required interrupt mask and global interrupt mask (IntEn, GlIntMsk).
MICmd, MIIData, and MIISts registers.
This may be needed to determine the amount of buffering to use.
pointers to the queues. No bus master activity is triggered by the enable, because the
enqueue registers are zero.
queues. No bus master activity is triggered by the enable because the enqueue register
is zero.
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9-37
9
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