EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 16

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

EP93xx User’s Guide
xvi
with SPO=0 and SPH=0 ..............................................................................................................................23-6
with SPO=1 and SPH=0 ..............................................................................................................................23-8
Figure 10-4. Edge-triggered DREQ Mode .................................................................................................10-17
Figure 11-1. USB Focus Areas ...................................................................................................................11-2
Figure 11-2. Communication Channels .......................................................................................................11-3
Figure 11-3. Typical List Structure ..............................................................................................................11-4
Figure 11-4. Interrupt Endpoint Descriptor Structure ..................................................................................11-5
Figure 11-5. Sample Interrupt Endpoint Schedule ......................................................................................11-6
Figure 11-6. USB Host Controller Block Diagram .......................................................................................11-9
Figure 12-1. 32-bit Read, 32-bit Memory, 0 Wait Cycles, RBLE = 1, WAITn Inactive.................................12-3
Figure 12-2. 32-bit Write, 32-bit Memory, 0 Wait Cycles, RBLE = 1, WAITn Inactive.................................12-3
Figure 12-3. 16-bit Read, 16-bit Memory, RBLE = 1, WAITn Active ...........................................................12-4
Figure 12-4. 16-bit Write, 16-bit Memory, RBLE = 1, WAITn Active ...........................................................12-4
Figure 12-5. Single PC Card Interface ........................................................................................................12-7
Figure 14-1. UART Block Diagram ..............................................................................................................14-3
Figure 14-2. UART Character Frame .........................................................................................................14-6
Figure 14-3. UART Character Frame ..........................................................................................................14-6
Figure 15-1. IrDA SIR Encoder/decoder Block Diagram .............................................................................15-2
Figure 15-2. IrDA Data Modulation (3/16) ...................................................................................................15-4
Figure 17-1. RZ1/NRZ Bit Encoding Example.............................................................................................17-9
Figure 17-2. 4PPM Modulation Encoding..................................................................................................17-14
Figure 17-3. 4PPM Modulation Example...................................................................................................17-15
Figure 17-4. IrDA (4.0 Mbps) Transmission Format ..................................................................................17-15
Figure 21-1. Architectural Overview of the I
Figure 21-2. Bit Clock Generation Example ...........................................................................................21-10
Figure 21-3. Frame Format for Right Justified Data ..................................................................................21-10
Figure 23-1. Texas Instruments Synchronous Serial Frame Format (Single Transfer)...............................23-4
Figure 23-2. TI Synchronous Serial Frame Format (Continuous Transfer) .................................................23-4
Figure 23-3. Motorola SPI Frame Format (Single Transfer) with SPO=0 and SPH=0 ................................23-5
Figure 23-4. Motorola SPI Frame Format (Continuous Transfer)
Figure 23-5. Motorola SPI Frame Format with SPO=0 and SPH=1 ............................................................23-7
Figure 23-6. Motorola SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ................................23-8
Figure 23-7. Motorola SPI Frame Format (Continuous Transfer)
Figure 23-8. Motorola SPI Frame Format with SPO=1 and SPH=1 ............................................................23-9
Figure 23-9. Microwire Frame Format (Single Transfer) ...........................................................................23-10
Figure 23-10. Microwire Frame Format (Continuous Transfers) ...............................................................23-12
Figure 23-11. Microwire Frame Format, SFRMIN Input Setup and Hold Requirements ...........................23-12
Figure 24-1. PWM_INV Example ................................................................................................................24-6
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S Controller ...........................................................................21-1
Copyright 2007 Cirrus Logic, Inc.
DS785UM1