EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 411
![IC ARM9 SOC PROCESSOR 208LQFP](/photos/12/23/122385/mfg_ep9302_parts_sml.jpg)
EP9302-CQZ
Manufacturer Part Number
EP9302-CQZ
Description
IC ARM9 SOC PROCESSOR 208LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9302-IQZ.pdf
(42 pages)
3.EP9302-IQZ.pdf
(4 pages)
4.EP9302-IQZ.pdf
(40 pages)
Specifications of EP9302-CQZ
Program Memory Type
ROMless
Package / Case
208-LQFP
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Data Ram Size
16 bit
Interface Type
USB, USART, SPI
Maximum Clock Frequency
200 MHz
Number Of Programmable I/os
37
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9302A-Z
Controller Family/series
(ARM9)
No. Of I/o's
19
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1132 - KIT DEVELOPMENT EP9302 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1137
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9302-CQZ
Manufacturer:
Cirrus
Quantity:
3 295
Company:
Part Number:
EP9302-CQZ
Manufacturer:
ALTERA
Quantity:
672
Part Number:
EP9302-CQZ
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
- EP9307-CRZ PDF datasheet
- EP9302-IQZ PDF datasheet #2
- EP9302-IQZ PDF datasheet #3
- EP9302-IQZ PDF datasheet #4
- Current page: 411 of 824
- Download datasheet (13Mb)
DS785UM1
10.1.11 DMA Data Transfer Size Determination
10.1.11.1 Software Initiated M2M and M2P/P2M Transfers
DREQ_SYNC1
DREQ_SYNC2
Data transfer size flexibility is guaranteed by allowing the start address of a DMA transfer to
be aligned to any arbitrary byte boundary since this is the case for the 10 internal byte-wide
M2P/P2M channels and for the 2 M2M channels when used in software initiated mode.
HCLK
EXDREQ
LATCH_DREQ
DREQ
DMA_STATE
1. A DREQ rising edge (DREQ is active high) is latched onto LATCH_DREQ during cycle
2. This signal is synchronized using 2 HCLK flip-flops. The DREQS status bit indicates a
3. The DMA state machine moves into the DMA_MEM_RD state to begin servicing the first
4. The DREQ latch is reset as a result of this state change and 2 cycles later the DREQS
5. A second request cannot be recognized until DREQS is cleared. Hence the request
6. A rising edge on DREQ during cycle 6 is latched and causes the DREQS status bit to be
1.
Subsequent changes on DREQ are ignored until the pending request begins to be
serviced. When the pending request has begun to be serviced, the DREQS status bit is
cleared and subsequent edge-triggered requests are again recognized (latched) by the
DMA. The DREQS status bit can be cleared by a software write to the channel STATUS
register, thus causing the DMA to ignore the request.
request is pending at start of cycle 3.
request in cycle 4.
status bit is cleared.
received during cycle 2 is ignored by the DMA.
set again, thus indicating that another external peripheral request is pending.
1
DMA_STALL
2
Figure 10-4. Edge-triggered DREQ Mode
Copyright 2007 Cirrus Logic
3
4
5
DMA_MEM_RD
6
7
EP93xx User’s Guide
8
DMA Controller
10-17
10
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