EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 424

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

10
CURRENTx
M2M Channel Register Map
10-30
DMA Controller
EP93xx User’s Guide
31
15
Address:
Definition:
Bit Descriptions:
The DMA Memory Map defines the mapping for the channel registers for each of the 2 M2M
channels that are shown in
common for each channel thus offset addresses are shown.
Note that M2M Channel 0 is dedicated to servicing External Device 0, and M2M Channel 1 is
dedicated to servicing External Device 1 (when in external DMA transfer mode).
30
14
Channel Base Address + 0x000C
Channel Base Address + 0x001C
Channel Base Address + 0x0000
Channel Base Address + 0x0004
Channel Base Address + 0x0008
Channel Base Address + 0x0010
Channel Base Address + 0x0014
Channel Base Address + 0x0018
Channel Base Address + 0x0020
Channel Base Address + 0x0024
29
13
28
12
CURRENT0: Channel Base Address + 0x0028 - Read Only
CURRENT1: Channel Base Address + 0x0038 - Read Only
This is the Channel Current Address Register.
CURRENTx:
Offset
27
11
Table 10-8. PPALLOC Register Reset Values
26
10
Table
Copyright 2007 Cirrus Logic
25
9
10-8, the M2M Channel Register Map. This mapping is
Returns the current value of the channel address pointer.
Upon enabling the DMA Channel and writing the BASE
Address Register the contents of this register is loaded
into the CURRENTx register and the x buffer becomes
active. Following completion of a transfer from a buffer, the
post-incremented address is stored in this register so that
a software service routine can detect the point in the buffer
at which transfer was terminated.
SAR_CURRENT0
INTERRUPT
SAR_BASE0
SAR_BASE1
CONTROL
Reserved
Reserved
STATUS
Name
24
CURRENTx
CURRENTx
BCR0
BCR1
8
23
7
22
6
Access
R/W TC*
R/W TC*
R/W
R/W
R/W
R/W
R/W
RO
21
5
Bits
32
14
16
16
32
32
32
3
20
4
Reset Value
19
3
0
0
0
0
0
0
0
0
18
2
17
1
DS785UM1
16
0