EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 568

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

15
UART2LinCtrlMid
15-10
UART2
EP93xx User’s Guide
31
15
Address:
Default:
30
14
29
13
28
12
FEN:
STP2:
EPS:
PEN:
BRK:
0x808D_000C - Read/Write
0x0000_0000
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
FIFO Enable.
1 - Transmit and receive FIFO buffers are enabled (FIFO
mode).
0 - The FIFOs are disabled (character mode). (That is, the
FIFOs become 1-byte-deep holding registers.)
Two Stop Bits Select.
1 - Two stop bits are transmitted at the end of the frame.
0 - One stop bit is transmitted at the end of the frame.
The receive logic does not check for two stop bits being
received.
Even Parity Select.
1 - Even parity generation and checking is performed
during transmission and reception (this checks for an even
number of “1”s in data and parity bits).
0 - Odd parity is performed (this checks for an odd number
of “1”s).
This bit has no effect when parity is disabled by Parity
Enable (bit 1) being cleared to 0.
Parity Enable.
1 - Parity checking and generation is enabled,
0 - Parity checking is disabled and no parity bit added to
the data frame.
Send Break.
1 - A low level is continually output on the UARTTXD
output, after completing transmission of the current
character. This bit must be asserted for at least one
complete frame transmission time in order to generate a
break condition. The transmit FIFO contents remain
unaffected during a break condition.
0 - For normal use, this bit must be cleared.
24
8
RSVD
23
7
22
6
21
5
20
4
BR
19
3
18
2
17
1
DS785UM1
16
0