EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 595

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

DS785UM1
Note: This bit reflects the status associated with the last character read from the RX FIFO. It
Note: This bit reflects the status associated with the last character read from the RX FIFO. It
changes with reads from the RX FIFO.
changes with reads from the RX FIFO.
RAB:
RTO:
EOF:
RFL:
RIL:
RFC:
RFS:
Copyright 2007 Cirrus Logic
Receiver Abort. (Read Only)
0 - No abort has been detected for the incoming frame.
1 - Abort detected during receipt of incoming frame. The
most recently read data is the last valid data before the
abort. EOF is also set.
Receiver Time Out.
Set to “1” whenever the HDLC RX has received four
consecutive flags, or four character times of idle or space.
Cleared by writing a “1” to this bit.
End of Frame (read only).
0 - Current frame has not been received completely.
1 - The data most recently read from the RX FIFO is the
last byte of data within the frame.
Receive Frame Lost. (Read/Write)
Set to “1” when an ROR occurred at the start of a new
frame, before any data for the frame could be put into the
RX FIFO. Cleared by writing a “1” to this bit.
Receive Information buffer Lost. (Read/Write)
Set to “1” when the last data for a frame is read from the
RX FIFO and the UART1HDLCRXInfoBuf has not been
read since the last data of the previous frame was read.
That is, the information loaded into the
UART1HDLCRXInfoBuf about the previous frame was
never read and has been overwritten. Cleared by writing a
“1” to this bit.
Received Frame Complete. (Read/Write)
Set to “1” when the last data byte for the frame is read
from the RX FIFO (this also triggers an update of the
UART1HDLCRXInfoBuf). Cleared by writing to a “1” to this
bit.
Receive FIFO Service request. (Read Only)
This bit is a copy of the RIS bit in the UART interrupt
identification register.
0 - RX FIFO is empty or RX is disabled.
1 - RX FIFO not empty and RX enabled.
May generate an interrupt and signal a DMA service
request.
UART3 With HDLC Encoder
EP93xx User’s Guide
16-19
16