EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 698

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

22
AC97TXCRx
22-10
AC’97 Controller
EP93xx User’s Guide
CM
31
15
Address:
Definition:
Bit Descriptions:
30
14
TSIZE
29
13
TX12
28
12
AC97TXCR1 - 0x8088_0008 - Read/Write
AC97TXCR2 - 0x8088_0028 - Read/Write
AC97TXCR3 - 0x8088_0048 - Read/Write
AC97TXCR4 - 0x8088_0068 - Read/Write
Transmit Control Registers. The AC97TXCR registers are read/write. The data
contained within the register controls the data slots that are contained within
the FIFO’s transmit register. The data within this FIFO must be of the same
sampling frequency, such as all audio slot data at 44.1 kHz. This register is
used to create slot 0 for transmitting. If this register specifies that the data
within is for Slot1 and 2, this will take precedence over the data in the
SLOT1TX and SLOT2TX register. If Slot 1 and 2 data is to be sent via this
FIFO, it will always be transmitted at 48kHz. Therefore, it is advisable not to
enable any other slots unless they too are sampled at 48kHz.
The data contained within the TSIZE bits controls the number of zeros that are
to be appended to data to make it 20 bits.
Should two channels be enabled for the same data slot, then data is taken
from/given to the lower channel number.
The data into the FIFO is stored in the lowest slot first. For example if the FIFO
is set up to store in slots 3 and 4, then slot 3 is the first data into the FIFO and
slot 4 the second.
RSVD:
FDIS:
TX11
27
11
TX10
26
10
Copyright 2007 Cirrus Logic
TX9
25
9
Reserved. Unknown During Read.
FIFO Disable
0 - The FIFO buffers are Enabled (FIFO mode).
1 - The FIFO is disabled (character mode). That is, the
FIFO becomes 1-byte-deep holding registers.
RSVD
TX8
24
8
TX7
23
7
TX6
22
6
TX5
21
5
TX4
20
4
TX3
19
3
TX2
18
2
TX1
17
1
DS785UM1
FDIS
TEN
16
0