EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 52

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

2
2-14
ARM920T Core and Advanced High-Speed Bus (AHB)
EP93xx User’s Guide
User mode in Thumb state limits access to the low registers r0-r7. To access to the high
registers, the ARM Core must first revert to the ARM state. The high registers are:
• r0-r12: General purpose read/write 32-bit registers
• r13 (sp): Stack Pointer
• r14 (lr): Link Register
• r15 (pc): Program Counter
• cpsr: Current Program Status Register containing condition codes and operating modes
r13(sp)
r15(pc)
r14(lr)
User
cpsr
r10
r12
r11
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
System
cpsr
r10
r11
r12
r13
r14
pc
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
Note: Colored areas represent banked registers.
Supervisor
Table 2-5. Register Organization Summary
spsr_svc
r13_svc
r14_svc
cpsr
r10
r11
r12
pc
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
Copyright 2007 Cirrus Logic
Privileged Modes
spsr_abt
r13_abt
r14_abt
Abort
cpsr
r10
r11
r12
pc
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
Exception Modes
Undefined
spsr_und
r13_und
r14_und
cpsr
r10
r12
r11
pc
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
spsr_irq
r13_irq
r14_irq
IRQ
cpsr
r10
r11
r12
pc
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
spsr_fiq
r10_fiq
r12_fiq
r13_fiq
r14_fiq
r11_fiq
r8_fiq
r9_fiq
FIQ
cpsr
pc
r0
r1
r2
r3
r4
r5
r6
r7
state high
state low
registers
registers
Thumb
Thumb
DS785UM1