EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 608

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

17
17-12
IrDA
EP93xx User’s Guide
receive buffer, ignores the remainder of the frame and begins to search for the stop flag. The
second byte of the frame can contain an optional control field that must be decoded in
software (There is no hardware support within the MIR). Use of a control byte is determined
by the user.
When the receive buffer contains a word of data, an interrupt or DMA request is signalled. If
the data is not removed soon enough and the buffer is completely filled, an overrun error is
generated when the receive logic attempts to place additional data into the full buffer. If this
occurs all subsequent data in the frame is discarded by the interface and the last valid entry
in the buffer is marked with the ROR and EOF bits. The interface will stall in this state until the
receive buffer is emptied.
Frames can contain any amount of data in multiples of 8 bits. Although the MIR protocol does
not limit frame size, in practice they tend to be implemented in numbers ranging from
hundreds to a couple of thousand bytes. In general this interface expects received frame size
to be limited to 2047 bytes. However, the interface can continue to operate past this limit
provided that software drivers are written that carefully check the indicated frame length with
the amount of data transferred (in the DMA case this is a little more difficult).
The receive logic continuously searches for the stop flag at the end of the frame. Once it is
recognized, the last byte that was placed within the receive buffer is flagged as the last byte
of the frame and the two bytes remaining within the temporary buffer are removed and used
as the 16 bit CRC value for the frame. Instead of placing this in the receive buffer, the receive
logic compares it to the CRC-CCITT value which is continuously calculated using the
incoming data stream. If they do not match, the last byte that was placed within the receive
buffer is also flagged with a CRC error. The CRC value is not placed in the receive buffer.
The MIR protocol permits back to back frames to be received. When this occurs, three flags
separate back to back frames.
Most commercial IrDA transceivers can generate an abort (7 to 13 ones) when their transmit
buffer underruns. The receive logic contains a counter that increments each time a one is
decoded before entering the serial shifter and is reset any time a zero is decoded. When
seven or more ones are detected, a receiver abort occurs. Note that data is moved from the
serial shifter to the temporary buffer a byte at a time and seven consecutive ones may bridge
two bytes. For this reason, after an abort is detected, the remaining data in the serial shifter is
discarded along with the most recent byte of data placed in the temporary buffer. After this
data is discarded, the oldest byte of data in the temporary buffer is placed in the receive
buffer, the EOF tag is set within the top entry of the buffer (next to the byte transferred from
the temporary buffer), the receiver abort interrupt is signalled and the receiver logic enters
hunt mode until it recognizes the next flag.
This interface also generates an abort condition when a stop flag is received that is not byte
aligned with the rest of the data in the frame. In this case the over flow data bits past the last
byte boundary are discarded. It is not possible for the programmer to distinguish this
condition for an normal abort condition.
If the user disables the receiver during operation, reception of the current data byte is
stopped immediately, the serial shifter and receive buffer are cleared and all clocks used by
the receive logic are automatically shut off to conserve power.
Copyright 2007 Cirrus Logic
DS785UM1