EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 101

IC ARM9 SOC PROCESSOR 208LQFP

EP9302-CQZ

Manufacturer Part Number
EP9302-CQZ
Description
IC ARM9 SOC PROCESSOR 208LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9302-CQZ

Program Memory Type
ROMless
Package / Case
208-LQFP
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Data Ram Size
16 bit
Interface Type
USB, USART, SPI
Maximum Clock Frequency
200 MHz
Number Of Programmable I/os
37
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9302A-Z
Controller Family/series
(ARM9)
No. Of I/o's
19
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1132 - KIT DEVELOPMENT EP9302 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1137

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DS785UM1
3.5.4 Copy and Conversion Instructions
31:28
31:28
31:28
cond
cond
cond
Description:
Mnemonic:
Bit Definitions:
Description:
Mnemonic:
Bit Definitions:
Description:
Mnemonic:
Bit Definitions:
1 1 1 0
1 1 1 0
1 1 1 0
27:24
27:24
27:24
Move from Control/Status Register to MaverickCrunch Register
Copy Single Precision Floating Point
Copy Double Precision Floating Point
Moves a 64-bit value from the MaverickCrunch Status/Control register,
DSPSC, to a MaverickCrunch register. CRn is ignored.
CFMV32SC<cond> CRd, CRn
CRd:
Copies a single precision floating point value from one register to another.
CFCPYS<cond> CRd, CRn
CRd:
CRn:
Copies a double precision floating point value from one register to another.
CFCPYD<cond> CRd, CRn
CRd:
CRn:
23:22
23:22
23:22
0 0
0 0
0 0
21:20
21:20
21:20
0 1
0 0
0 0
Copyright 2007 Cirrus Logic
Destination register
Destination register
Source register
Destination register
Source register
19:16
19:16
19:16
CRn
CRn
CRn
15:12
15:12
15:12
CRd
CRd
CRd
0 1 0 0
0 1 0 0
0 1 0 0
11:8
11:8
11:8
MaverickCrunch Co-Processor
1 1 1
0 0 0
0 0 1
7:5
7:5
7:5
EP93xx User’s Guide
4
4
4
0
0
0
CRm
CRm
CRm
3:0
3:0
3:0
3-31
3

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