EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 344

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

9
9-42
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
Chip Reset:
Rx Reset:
Soft Reset:
Definition:
Bit Descriptions:
Note: The IA field of the table means the same Individual Addresses as RxFCE, that is, IA0
implies RxFCE0 and IA1 implies RxFCE1
Individu
Accept
IA[1:0]
al
0
1
1
1
Table 9-4. Individual Accept, RxFlow Control Enable and Pause Accept Bits
0x0000_0x0x
0x0000_0000
0x0000_0000
Receiver Control Register. The Receive Control register is reset by Rx Reset
signal generated by holding the TESTSELn pin low. The same signal is also
used to reset the receive MAC. The purpose of having a separate reset signal
is to be able to avoid resetting the receive MAC when the AHB bus is in a
powered down state (RESET active), and wake-up frames need to be
detected.
RSVD:
PauseA:
RxFCE[1:
Receive
Control
Enable
Flow
0]
X
1
1
0
Copyright 2007 Cirrus Logic
PauseA
Accept
Pause
X
X
0
1
Reserved. Unknown During Read.
Pause Accept. When set, Pause frames are passed on to
the Host as regular frames. When clear, the frames are
discarded. The handling of MAC Control frames depends
on the Pause Accept bit as well as the appropriate
Individual Accept and RxFlow Control Enable bits, as
follows.
Frame discarded (do not pass the address filter)
MAC Control frames are recognized, flow control action taken,
and frames not passed to host. Non pause MAC Control
frames are passed on to host.
MAC Control frames are recognized, flow control action taken,
and all MAC control frames are passed on to host.
MAC Control frames are not distinguished from other frame
types, all frames passed on to host.
Action
DS785UM1