EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 586

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

16
UART3IntIDIntClr
16-10
UART3 With HDLC Encoder
EP93xx User’s Guide
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
BUSY:
DCD:
DSR:
CTS:
0x808E_001C - Read/Write
0x0000_0000
UART3 Interrupt Identification and Interrupt Clear Register. Interrupt status is
read from UART3IntIDIntClr. A write to UART3IntIDIntClr clears the modem
status interrupt. All the bits are cleared to “0” when reset.
RSVD:
RTIS:
27
11
26
10
RSVD
Copyright 2007 Cirrus Logic
25
9
UART Busy. If this bit is set to 1, the UART is busy
transmitting data. This bit remains set until the complete
byte, including all the stop bits, has been sent from the
shift register. This bit is set as soon as the transmit FIFO
becomes non-empty, regardless of whether the UART is
enabled or not.
Data Carrier Detect status. This bit is the complement of
the UART data carrier detect (nUARTDCD) modem status
input. That is, the bit is 1 when the modem status input is
0.
Data Set Ready status. This bit is the complement of the
UART data set ready (nUARTDSR) modem status input.
That is, the bit is 1 when the modem status input is 0.
Clear To Send status. This bit is the complement of the
UART clear to send (nUARTCTS) modem status input.
That is, the bit is 1 when the modem status input is 0.
Reserved. Unknown During Read.
Receive Timeout Interrupt Status. This bit is set to 1 if the
receive timeout interrupt is asserted. This bit is cleared
when the receive FIFO is empty or the receive line goes
active.
24
8
RSVD
23
7
22
6
21
5
20
4
RTIS
19
3
TIS
18
2
RIS
17
1
DS785UM1
MIS
16
0