EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 458

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

11
HcInterruptEnable
11-18
Universal Serial Bus Host Controller
EP93xx User’s Guide
MIE
31
15
Address:
Default:
Definition:
Bit Descriptions:
OC
30
14
29
13
28
12
FNO:
RHSC:
OC:
0x8002_0010
0x0000_0000
Enables interrupt sources.
RSVD:
SO:
WDH:
SF:
RD:
UE:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
FrameNumberOverflow. This bit is set when the MSB of
HcFmNumber (bit 15) changes value, from 0 to 1 or from 1
to 0, and after HccaFrameNumber has been updated.
RootHubStatusChange. This bit is set when the content of
HcRhStatus or the content of any of
HcRhPortStatus[NumberofDownstreamPort] has changed.
OwnershipChange. This bit is set by HC when HCD sets
the OwnershipChangeRequest field in
HcCommandStatus. This event, when unmasked, will
always generate a System Management Interrupt (SMI)
immediately. This bit is tied to 0b when the SMI pin is not
implemented.
Reserved. Unknown During Read.
SchedulingOverrun. Enable interrupt generation due to
Scheduling Overrun.
WritebackDoneHead. Enable interrupt generation due to
HcDoneHead Writeback.
StartofFrame. Enable interrupt generation due to Start of
Frame.
ResumeDetected. Enable interrupt generation due to
Resume Detect.
UnrecoverableError. Enable interrupt generation due to
Unrecoverable Error.
24
8
23
7
RSVD
RHSC
22
6
FNO
21
5
UE
20
4
RD
19
3
SF
18
2
WDH
17
1
DS785UM1
SO
16
0