EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 620

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

17
IrCtrl
17-24
IrDA
EP93xx User’s Guide
31
15
Address:
Default:
Definition:
Bit Descriptions:
Note: While the FIR transmit section is enabled, the FD bit is low, and while the MIR transmit
30
14
section is enabled, the MD bit is low. In FIR mode, the FD bit does not go high until the TXE
bit in the IrCtrl register is cleared, and in MIR mode, the same bit must be cleared for MD to
go high. Monitor the TBY bit in the IrFlag register to discover whether a packet is fully
transmitted before clearing TXE.
29
13
28
12
EN:
0x808B_0004
0x0000_0000
IrDA Control Register. This register selects various operating parameters.
Note that the RXE and TXE bit must be cleared before selecting a different
interface with the IrEnable register EN bits. The other bits in this register may
be changed while the interface is active.
RSVD:
AME:
RXP:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Enable value:
00 - No encoder selected
01 - SIR, 0 to 0.1152Mbit/s data rate, using the UART2
interface
10 - MIR, 0.576 or 1.152Mbit/s data rate, using IrDA
interface
11 - FIR, 4.0Mbit/s data rate, using IrDA interface.
Reserved. Unknown During Read.
Address Match Enable.
0 - Disable receiver address match function, store data
from all incoming frames in the receive buffer.
1 - Enable receiver address match function, do not buffer
data unless address is recognized or incoming address
contains all ones.
Receive Polarity Control.
0 - Data input is not inverted before decoding.
1 - Data input is inverted before decoding.
24
8
RSVD
AME
23
7
RXP
22
6
TXP
21
5
RXE
20
4
TXE
19
3
TUS
18
2
BRD
17
1
DS785UM1
16
0
0