EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 105

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

DS785UM1
3.5.5 Shift Instructions
31:28
31:28
cond
cond
Bit Definitions:
Description:
Mnemonic:
Bit Definitions:
Definition:
Mnemonic:
Bit Definitions:
1 1 1 0
1 1 1 0
27:24
27:24
Shift 32-bit Integer
Shift 64-bit Integer
CRd:
CRn:
Shifts a 32-bit integer left or right. The shift count is a two’s complement
integer stored in an ARM register; the count is positive for left shifts and
negative for right shifts. This instruction may also be used to copy a 32-bit
integer from one register to another by using a shift value of 0.
CFRSHL32<cond> CRm, CRn, Rd
CRm:
CRn:
Rd:
Shifts a 64-bit integer left or right. The shift count is a two’s complement
integer stored in an ARM register; the count is positive for left shifts and
negative for right shifts. This instruction may also be used to copy a 64-bit
integer from one register to another using a shift value of 0.
CFRSHL64<cond> CRm, CRn, Rd
CRm:
CRn:
Rd:
23:22
23:22
0 0
0 0
21
21
0
0
Copyright 2007 Cirrus Logic
20
20
0
0
Destination register
Source register
Destination register
Source register
Shift count register in ARM
Destination register
Source register
Shift count register in ARM
19:16
19:16
CRn
CRn
15:12
15:12
Rd
Rd
0 1 0 1
0 1 0 1
11:8
11:8
MaverickCrunch Co-Processor
0 1 0
0 1 1
7:5
7:5
EP93xx User’s Guide
4
1
4
1
CRm
CRm
3:0
3:0
3-35
3