EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 400
![IC ARM9 SOC PROCESSOR 208LQFP](/photos/12/23/122385/mfg_ep9302_parts_sml.jpg)
EP9302-CQZ
Manufacturer Part Number
EP9302-CQZ
Description
IC ARM9 SOC PROCESSOR 208LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9302-IQZ.pdf
(42 pages)
3.EP9302-IQZ.pdf
(4 pages)
4.EP9302-IQZ.pdf
(40 pages)
Specifications of EP9302-CQZ
Program Memory Type
ROMless
Package / Case
208-LQFP
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Data Ram Size
16 bit
Interface Type
USB, USART, SPI
Maximum Clock Frequency
200 MHz
Number Of Programmable I/os
37
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9302A-Z
Controller Family/series
(ARM9)
No. Of I/o's
19
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1132 - KIT DEVELOPMENT EP9302 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1137
Available stocks
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Price
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EP9302-CQZ
Manufacturer:
Cirrus
Quantity:
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EP9302-CQZ
Manufacturer:
ALTERA
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- EP9307-CRZ PDF datasheet
- EP9302-IQZ PDF datasheet #2
- EP9302-IQZ PDF datasheet #3
- EP9302-IQZ PDF datasheet #4
- Current page: 400 of 824
- Download datasheet (13Mb)
10
for External Peripherals without Handshaking Signals
Signals
10-6
DMA Controller
EP93xx User’s Guide
10.1.5.2 Hardware Trigger Mode for Internal Peripherals (SSP and IDE) and
10.1.5.3 Hardware Trigger Mode for External Peripherals with Handshaking
10.1.6 AHB Slave Interface Limitations
10.1.7 Interrupt Interface
10.1.8 Internal M2P/P2M Data Unpacker/Packer Functional Description
When a M2M channel is set up to transfer to/from SSP, IDE or an external peripheral, the
transfer width used (that is, the AMBA HSIZE signal) is determined by the peripheral width -
programmed via the CONTROL.PW bits of the channel. This means that the transfers occur
one at a time, as opposed to burst transfer operation for software triggered M2M. Thus the
16-byte data bay which is available for software triggered transfers is never fully utilized - at
most 1 word of it is used (depending on PW bits).
When a M2M channel is set up to transfer to/from an external peripheral, the transfer width
used (that is, the AMBA HSIZE signal) is determined by the peripheral width - programmed
via the CONTROL.PW bits of the channel. This means that the transfers occur one at a time,
as opposed to burst transfer operation for software triggered M2M. Thus the 16-byte data bay
which is available for software triggered transfers is never fully utilized - at most 1 word of it is
used (depending on PW bits).
The AHB slave interface is used to access all control and status registers.
The behavior of the AMBA AHB signals complies with the standard described in AMBA
Specification (Rev 2.0) from ARM Limited. The DMA does not utilize the AHB slave split
capabilities, so does not receive HMASTER or HMASTERLOCK and does not drive HSPLIT.
It does not receive HPROT or HRESP and does not drive HLOCK.
Each of the 12 DMA channels (10 M2P/P2M and 2 M2M) generates a single interrupt signal
which is a combination of the interrupt sources for that channel. There are 3 interrupt
sources, which are enabled in the channel control register (for both M2P/P2M and M2M):
DONE, STALL and NFB.The interrupt signals are ORed before being transmitted to the
DMA_INT output bus. Status of the interrupt bus is reflected in the DMA Global Interrupt
Register (DMAGlInt). The status of each interrupt source per channel is found in the
channel’s interrupt register.
The DMA controller transfers data to and from the system memory in four word bursts. The
peripheral DMA bus protocol is used to transfer data to and from the peripherals as single
bytes. In order to build the quad word bursts from the single bytes received from the
peripheral, the DMA controller uses the Rx Burst Packers. To decompose the quad word
bursts into byte transfers to the peripherals the Tx Burst Un-Packers are used.
Copyright 2007 Cirrus Logic
DS785UM1
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