EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 304

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

9
9-2
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9.1.1.2 Reset and Initialization
9.1.1.3 Power-down Modes
9.1.1.4 Address Space
The Descriptor Processor implements the Hardware Adapter Interface Algorithm and
generates transfer requests to the AHB Interface Controller. The back-end interfaces to the
MAC controllers and services MAC requests to run accesses to the FIFO and update queue
status. The Descriptor Processor also generates internal requests for descriptor fetches. A
priority arbiter arbitrates among the various requests and generates transfer requests to the
AHB Interface Controller. There are 6 queues that require service in system memory:
Each queue generates a hard request (for urgent service) and a soft request (not urgent, but
queue can run transfers). The priority assigned to the queues varies depending on the state
of the system, but hard requests are prioritized over soft requests, and AHB write requests
are prioritized over AHB read requests to allow faster back-to-back transfers.
The Ethernet LAN Controller has three reset sources: the AHB reset, software reset from the
SelfCtl register, and individual channel resets via the BMCtl register. The PHY is reset with
the PHYRES function in compliance with the 802.3 specifications and has no effect on the
MAC layer and up.
AHB reset initializes the entire controller, except for the receive MAC. The receive MAC is
initialized by a SOFT_RESET. Upon AHB reset the AHB Interface and Descriptor Processor
is put into a quiescent state.
Software Reset generates a SOFT_RESET which resets the Descriptor Processor, FIFO,
and MAC. SOFT_RESET occurring in the middle of a frame transmission will result in the
transmitted frame being truncated on the line. SOFT_RESET occurring in the middle of a
received frame will result in the reset of the frame being dropped. The configuration registers
remain intact during a soft reset. A SOFT_RESET should be issued following a power-on to
ensure the receive MAC is fully initialized.
The only power-down option is to stop the TXCLK and RXCLK by disabling the PHY.
The Address space is mapped as:
MACBase + 0x0000 - MACBase + 0x00FF: MAC setup registers.
MACBase + 0x0100 - MACBase + 0x011F: MAC configuration registers, only first 4 words
used.
• RxData: Write received frame data to host memory.
• RxStatus: Write received frame status to host memory.
• TxData: Read frame data from host memory.
• TxStatus: Write transmitted frame status to host memory.
• RxDescriptor: Read descriptors from host memory.
• TxDescriptor: Read descriptors from host memory.
Copyright 2007 Cirrus Logic
DS785UM1