EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 201
![IC ARM9 SOC PROCESSOR 208LQFP](/photos/12/23/122385/mfg_ep9302_parts_sml.jpg)
EP9302-CQZ
Manufacturer Part Number
EP9302-CQZ
Description
IC ARM9 SOC PROCESSOR 208LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9302-IQZ.pdf
(42 pages)
3.EP9302-IQZ.pdf
(4 pages)
4.EP9302-IQZ.pdf
(40 pages)
Specifications of EP9302-CQZ
Program Memory Type
ROMless
Package / Case
208-LQFP
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Data Ram Size
16 bit
Interface Type
USB, USART, SPI
Maximum Clock Frequency
200 MHz
Number Of Programmable I/os
37
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9302A-Z
Controller Family/series
(ARM9)
No. Of I/o's
19
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1132 - KIT DEVELOPMENT EP9302 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1137
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9302-CQZ
Manufacturer:
Cirrus
Quantity:
3 295
Company:
Part Number:
EP9302-CQZ
Manufacturer:
ALTERA
Quantity:
672
Part Number:
EP9302-CQZ
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
- EP9307-CRZ PDF datasheet
- EP9302-IQZ PDF datasheet #2
- EP9302-IQZ PDF datasheet #3
- EP9302-IQZ PDF datasheet #4
- Current page: 201 of 824
- Download datasheet (13Mb)
DS785UM1
D18
Fra
me
Ctr
X
X
At clock 0, the HCNT, VCNT and FRAME counters are 0x0. The pixel to display is a 5, which
translates to register base + 0x94, bit D0. At the next clock tick, the fastest running counter
(HCNT) has incremented, but VCNT and FRAME remain the same. Given the same pixel
value (5), bit position D1 is used as the value that is sent to the display.
Ve
17
Ct
rt
D
X
X
r
Ctr
Ho
D1
rz
6
X
X
Clock
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
address
register
(pixels)
(lines)
VCNT
HCNT
base +
base +
base +
base +
base +
base +
base +
base +
0x1C
0x3C
0x5C
0x7C
0x00
0x20
0x40
0x60
HCNT
3
0
1
2
3
0
1
2
3
0
1
2
3
“
“
“
15
11
11
D
0
0
0
0
1
1
1
1
Table 7-5. Grayscale Timing Diagram (Continued)
VCNT
11
10
14
D
0
0
0
0
1
1
1
1
Copyright 2007 Cirrus Logic
3
0
0
0
0
0
0
0
0
0
0
0
0
“
“
“
01
13
11
D
0
0
0
0
1
1
1
1
Table 7-6. Programming Format
Raster Engine With Analog/LCD Integrated Timing and Interface
11
00
12
D
0
0
0
0
1
1
1
1
FRAME
0
1
1
1
1
2
2
2
2
3
3
3
3
“
“
“
10
11
11
D
0
0
0
0
1
1
1
1
D1
10
10
0
0
0
0
0
1
1
1
1
PIXEL
D
1
0
0
1
9
0
0
0
0
1
1
1
1
5
5
5
5
5
5
5
5
5
5
5
5
5
“
“
“
1
0
0
0
D
8
0
0
0
0
1
1
1
1
0
1
1
1
D
7
0
0
0
0
1
1
1
1
D
0
1
1
0
6
0
0
0
0
1
1
1
1
Register Address / Value
D
0
1
0
1
5
0
0
0
0
1
1
1
1
(base + 94) / D15
(base + b4) / D0
(base + b4) / D1
(base + b4) / D2
(base + b4) / D3
(base + d4) / D0
(base + d4) / D1
(base + d4) / D2
(base + d4) / D3
(base + f4) / D0
(base + f4) / D1
(base + f4) / D2
(base + f4) / D3
0
1
0
0
D
4
0
0
0
0
1
1
1
1
0
0
1
1
D
3
0
0
0
0
1
1
1
1
0
0
1
0
D
2
0
0
0
0
1
1
1
1
EP93xx User’s Guide
D
0
0
0
1
1
0
0
0
0
1
1
1
1
D
0
0
0
0
0
0
0
0
0
1
1
1
1
GrySclLU
Address
Frame
*4
00
01
10
11
00
01
10
11
T
7-19
Pix
000
000
000
000
Val
111
111
111
111
ue
el
7
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