EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 245

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

Blink Control Registers
BlinkRate
BlinkMask
DS785UM1
31
15
31
15
Address: 0x8003_0040
Default: 0x0000_0000
Definition: Blink Rate Control register
Bit Descriptions:
Address: 0x8003_0044
Default: 0x0000_0000
Definition: Blink Mask register
30
14
30
14
29
13
29
13
28
12
28
12
RSVD:
RATE:
This register is used in conjunction with the
which pixels that are fetched from SDRAM are blink pixels.
RSVD
RSVD
27
11
27
11
26
10
26
10
Copyright 2007 Cirrus Logic
25
25
9
9
Reserved - Unknown during read
Rate - Read/Write
The blink rate value that is written to this field controls the
number of video frames that occur before the LUT
addresses assigned to ‘blink’ change between masked
and unmasked (see
on/off blink cycle is controlled by this equation:
Blink Cycle = 2 x (1/VCLK) x HClkTotal x VLinesTotal x
(255 - BlinkRate)
Raster Engine With Analog/LCD Integrated Timing and Interface
24
24
8
8
MASK
RSVD
23
23
7
7
22
22
6
6
“Blink Function” on page
21
21
5
5
BlinkPattrn
20
20
4
4
MASK
RATE
register to determine
19
19
3
3
EP93xx User’s Guide
18
18
2
2
7-10). The
17
17
1
1
16
16
7-63
0
0
7