r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 839

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

(3)
In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when
MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, refer to
figure 16.15. The reception procedure and operations in receive mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting)
2. When the transfer clock is output, set MST to 1 to start outputting the receive clock.
3. When the receive operation is completed, data is transferred from ICDRS to ICDRR and
4. To stop receiving when MST = 1, set RCVD in ICCR1 to 1, then read ICDRR. Then, SCL is
processing
(Output)
ICDRS
ICDRT
TDRE
TRS
SCL
SDA
User
RDRF in ICSR is set. When MST = 1, the next byte can be received, so the clock is
continually output. The continuous reception is performed by reading ICDRR every time
RDRF is set. When the 8th clock is risen while RDRF is 1, the overrun is detected and
AL/OVE in ICSR is set. At this time, the previous reception data is retained in ICDRR.
fixed high after receiving the next byte data.
Receive Operation
[2] Set TRS
[3] Write data
to ICDRT
Data 1
Bit 0
Figure 16.14 Transmit Mode Operation Timing
1
[3] Write data
to ICDRT
Bit 1
2
Data 1
Bit 6
7
Data 2
Bit 7
8
Bit 0
Data 2
1
Rev. 2.00 Dec. 09, 2005 Page 815 of 1152
Section 16 I
Bit 6
7
[3] Write data
Bit 7
to ICDRT
2
8
C Bus Interface 3 (IIC3)
REJ09B0191-0200
Data 3
[3] Write data
Bit 0
to ICDRT
1