r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 148

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 5 Interrupt Controller (INTC)
5.3.8
IBCR is a 16-bit register that enables or disables use of register banks for each interrupt priority
level. IBCR is initialized to H'0000 by a power-on reset.
Initial value:
Rev. 2.00 Dec. 09, 2005 Page 124 of 1152
REJ09B0191-0200
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W:
Bit:
Bank Control Register (IBCR)
Bit Name
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1

R/W
E15
15
0
R/W
E14
14
0
R/W
E13
13
0
Initial
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
E12
12
0
R/W
E11
11
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
E10
10
0
Description
Enable
These bits enable or disable use of register banks for
interrupt priority levels 15 to 1. However, use of register
banks is always disabled for the user break interrupts.
0: Use of register banks is disabled
1: Use of register banks is enabled
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W
E9
9
0
R/W
E8
8
0
R/W
E7
7
0
R/W
E6
6
0
R/W
E5
5
0
R/W
E4
4
0
R/W
E3
3
0
R/W
E2
2
0
R/W
E1
1
0
R
0
0
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