r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 27

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Items
Cache memory
Interrupt controller
(INTC)
Bus state controller
(BSC)
Specification
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Instruction cache: 8 Kbytes
Operand cache: 8 Kbytes
128-entry, 4-way set associative, 16-byte block length configuration
each for the instruction cache and operand cache
Write-back, write-through, LRU replacement algorithm
Cache lock function available (only for operand cache); ways 2 and 3
can be locked
Seventeen external interrupt pins (NMI, IRQ7 to IRQ0, and PINT7 to
PINT0)
On-chip peripheral interrupts: Priority level set for each module
16 priority levels available
Register bank enabling fast register saving and restoring in interrupt
processing
Address space divided into nine areas (0 to 8), each a maximum of 64
Mbytes
The following features settable for each area independently
 Bus size (8, 16, or 32 bits): Available sizes depend on the area.
 Number of access wait cycles (different wait cycles can be
 Idle wait cycle insertion (between same area access cycles or
 Specifying the memory to be connected to each area enables
 PCMCIA interface
 Outputs a chip select signal (CS0 to CS8) according to the target
SDRAM refresh
Auto refresh or self refresh mode selectable
SDRAM burst access
specified for read and write access cycles in some areas)
different area access cycles)
direct connection to SRAM, SRAM with byte selection, SDRAM,
and burst ROM (clocked synchronous or asynchronous). The
address/data multiplexed I/O (MPX) interface and burst MPX-I/O
interface are also available.
area (CS assert or negate timing can be selected by software)
Rev. 2.00 Dec. 09, 2005 Page 3 of 1152
Section 1 Overview
REJ09B0191-0200