r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 757

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Bit
4
3
Bit Name
RE
REIE
Initial
Value
0
0
R/W
R/W
R/W
Description
Receive Enable
Enables or disables the serial receiver.
0: Receiver disabled*
1: Receiver enabled*
Notes: 1. Clearing RE to 0 does not affect the receive
Receive Error Interrupt Enable
Enables or disables the receive-error (ERI) interrupts
and break (BRI) interrupts. The setting of REIE bit is
valid only when RIE bit is set to 0.
0: Receive-error interrupt (ERI) and break interrupt
1: Receive-error interrupt (ERI) and break interrupt
Note: * ERI or BRI interrupt requests can be cleared by
Section 15 Serial Communication Interface with FIFO (SCIF)
(BRI) requests are disabled
(BRI) requests are enabled*
2. Serial reception starts when a start bit is
reading the ER, BR or ORER flag after it has
been set to 1, then clearing the flag to 0, or by
clearing RIE and REIE to 0. Even if RIE is set
to 0, when REIE is set to 1, ERI or BRI
interrupt requests are enabled. Set so If SCIF
wants to inform INTC of ERI or BRI interrupt
requests during DMA transfer.
flags (DR, ER, BRK, RDF, FER, PER, and
ORER). These flags retain their previous
values.
detected in asynchronous mode, or
synchronous clock is detected in clocked
synchronous mode. Select the receive format
in SCSMR and SCFCR and reset the receive
FIFO before setting RE to 1.
Rev. 2.00 Dec. 09, 2005 Page 733 of 1152
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