r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 1161

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Item
10.3.6 Timer Status Register
(TSR)
•
10.4.10 MTU2–MTU2S
Synchronous Operation
(b) Examples of Synchronous
Counter Start Operation
TSR_5
Page Revision (See Manual for Details)
455
to
457
578
Amended.
Notes:
Amended and added.
Figures 10.84 (1) to (4) show examples of synchronous
counter start operation when the clock frequency ratios
between the MTU2 and MTU2S are 1:1, 1:2, 1:3, and
1:4, respectively. In these examples, the count clock is
set to Pφ/1.
Bit
2
1
0
Bit Name R/W
CMFU5
CMFV5
CMFW5
1. Writing 0 to this bit after reading it as 1 clears the
2. Timing for transfer is set by the IOC bit in the
flag and is the only allowed way.
timer I/O control register U_5/V_5/W_5
(TIORU_5/V_5/W_5).
Rev. 2.00 Dec. 09, 2005 Page 1137 of 1152
R/(W)*
R/(W)*
R/(W)*
1
1
1
Description
[Setting conditions]
•
[Setting conditions]
•
[Setting conditions]
•
When TCNTU_5 value is
transferred to TGRU_5 and
TGRU_5 is functioning as a
register for measuring the
pulse width of the external
input signal. The transfer
timing is specified by the
IOC bits in timer I/O control
registers U_5, V_5, and
W_5 (TIORU_5, TIORV_5,
and TIORW_5).*
When TCNTV_5 value is
transferred to TGRV_5 and
TGRV_5 is functioning as a
register for measuring the
pulse width of the external
input signal. The transfer
timing is specified by the
IOC bits in timer I/O control
registers U_5, V_5, and
W_5 (TIORU_5, TIORV_5,
and TIORW_5).*
When TCNTW_5 value is
transferred to TGRW_5 and
TGRW_5 is functioning as
a register for measuring the
pulse width of the external
input signal.*
REJ09B0191-0200
2
2
2