r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 1158

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Rev. 2.00 Dec. 09, 2005 Page 1134 of 1152
REJ09B0191-0200
Item
9.3.4 DMA Channel Control
Registers (CHCR)
9.4.5 Number of Bus Cycles and
DREQ Pin Sampling Timing
Page Revision (See Manual for Details)
371
405
Note deleted.
Amended and added.
The unit of the DMA transfer is divided into multiple bus
cycles when 16-byte transfer is performed for an 8-bit,
16-bit, or 32-bit external device, when longword access
is performed for an 8-bit or 16-bit external device, or
when word access is performed for an 8-bit external
device. When a setting is made so that the DMA
transfer size is divided into multiple bus cycles and the
CS signal is negated between bus cycles, note that
DACK and TEND are divided like the CS signal for data
alignment as shown in figure 9.18. Also, the DREQ
sampling may not be detected correctly with divided
DACK, and one extra overrun may occur at maximum.
Use a setting that does not divide DACK or specify a
transfer size smaller than the external device bus width
if DACK is divided.
Bit
16
Bit Name Description
AL
Acknowledge Level
Specifies the DACK (acknowledge) signal
output is high active or low active.
This bit is valid only in CHCR_0 to
CHCR_3. This bit is reserved in CHCR_4
to CHCR_7; it is always read as 0 and
the write value should always be 0.
0: Low-active output from DACK
1: High-active output from DACK
Note: When selecting high-active output
for DACK, pull down the DACK pin
and specify the pin function by the
following procedure.
1. After starting the LSI by a reset,
2. Then, select the DACK pin
3. After the above setting is
select high active output for the
DACK pin by CHCR in the
DMAC.
function in the pin function
controller.
completed, do not modify the
DACK pin setting in CHCR.