r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 753

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Bit
5
4
Bit Name
PE
O/E
Initial
Value
0
0
R/W
R/W
R/W
Description
Parity Enable
Selects whether to add a parity bit to transmit data and
to check the parity of receive data, in asynchronous
mode. In clocked synchronous mode, a parity bit is
neither added nor checked, regardless of the PE setting.
0: Parity bit not added or checked
1: Parity bit added and checked*
Note: * When PE is set to 1, an even or odd parity bit is
Parity mode
Selects even or odd parity when parity bits are added
and checked. The O/E setting is used only in
asynchronous mode and only when the parity enable bit
(PE) is set to 1 to enable parity addition and checking.
The O/E setting is ignored in clocked synchronous
mode, or in asynchronous mode when parity addition
and checking is disabled.
0: Even parity*
1: Odd parity*
Notes: 1. If even parity is selected, the parity bit is
Section 15 Serial Communication Interface with FIFO (SCIF)
2. If odd parity is selected, the parity bit is added
added to transmit data, depending on the parity
mode (O/E) setting. Receive data parity is
checked according to the even/odd (O/E) mode
setting.
added to transmit data to make an even
number of 1s in the transmitted character and
parity bit combined. Receive data is checked
to see if it has an even number of 1s in the
received character and parity bit combined.
to transmit data to make an odd number of 1s
in the transmitted character and parity bit
combined. Receive data is checked to see if it
has an odd number of 1s in the received
character and parity bit combined.
2
1
Rev. 2.00 Dec. 09, 2005 Page 729 of 1152
REJ09B0191-0200