r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 35

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Classification
Interrupts
Address bus
Data bus
Bus control
Symbol
NMI
IRQ7 to IRQ0
PINT7 to PINT0 I
IRQOUT
A25 to A0
D31 to D0
CS8 to CS0
RD
RD/WR
BS
AH
FRAME
WAIT
WE0
I/O
I
I
O
O
I/O
O
O
O
O
O
O
I
O
Name
Non-maskable
Interrupt request
output
Chip select 8 to 0 Chip-select signals for external
Read
Read/write
Bus start
Address hold
Wait
Byte select
interrupt
Interrupt requests
7 to 0
Interrupt requests
7 to 0
Address bus
Data bus
FRAME signal
Rev. 2.00 Dec. 09, 2005 Page 11 of 1152
Function
Non-maskable interrupt request pin.
Fix it high when not in use.
Maskable interrupt request pins.
Level-input or edge-input detection
can be selected. When the edge-
input detection is selected, the rising
edge, falling edge, or both edges can
also be selected.
Maskable interrupt request pins.
Only level-input detection can be
selected.
Indicates that an interrupt has
occurred, enabling external devices
to be informed of an interrupt
occurrence even while the bus
mastership is released.
Outputs addresses.
Bidirectional data bus.
memory or devices.
Indicates that data is read from an
external device.
Read/write signal.
Bus-cycle start signal.
Address hold timing signal for the
device that uses the address/data-
multiplexed bus.
Connected to the FRAME signal in
the burst MPX-I/O interface.
Input signal for inserting a wait cycle
into the bus cycles during access to
the external space.
Indicates a write access to bits 7 to 0
of data of external memory or
device.
Section 1 Overview
REJ09B0191-0200