r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 293

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 8 Bus State Controller (BSC)
read in case of a 32-bit device, and 16 bits in case of a 16-bit device. When writing, only the WEn
signal for the byte to be written is asserted.
It is necessary to output the data that has been read using RD when a buffer is established in the
data bus. The RD/WR signal is in a read state (high output) when no access has been carried out.
Therefore, care must be taken when controlling the external data buffer, to avoid collision.
Figures 8.4 and 8.5 show the basic timings of normal space access. If the WM bit in CSnWCR is
cleared to 0, a Tnop cycle is inserted after the CSn space access to evaluate the external wait
(figure 8.4). If the WM bit in CSnWCR is set to 1, external waits are ignored and no Tnop cycle is
inserted (figure 8.5).
T1
T2
Tnop
T1
T2
CKIO
A25 to A0
CSn
RD/WR
RD
Read
D15 to D0
WEn
Write
D15 to D0
BS
*
DACKn
WAIT
Note: * The waveform for DACKn is when active low is specified.
Figure 8.4 Continuous Access for Normal Space 1
Bus Width = 16 Bits, Longword Access, CSnWCR.WM Bit = 0
(Access Wait = 0, Cycle Wait = 0)
Rev. 2.00 Dec. 09, 2005 Page 269 of 1152
REJ09B0191-0200