r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 534

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r5s72060w200fpv

Manufacturer Part Number
r5s72060w200fpv
Description
32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet

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0
Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
(3)
Figure 10.22 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the
I2AE bit in TICCR has been set to 1 to include the TIOC2A pin in the TGRA_1 input capture
conditions. In this example, the IOA0 to IOA3 bits in TIOR_1 have selected the TIOC1A rising
edge for the input capture timing while the IOA0 to IOA3 bits in TIOR_2 have selected the
TIOC2A rising edge for the input capture timing.
Under these conditions, the rising edge of both TIOC1A and TIOC2A is used for the TGRA_1
input capture condition. For the TGRA_2 input capture condition, the TIOC2A rising edge is used.
Rev. 2.00 Dec. 09, 2005 Page 510 of 1152
REJ09B0191-0200
TGRA_1
TGRA_2
TCNT_1
TIOC1A
TIOC2A
H'FFFF
H'C256
H'6128
H'0000
Cascaded Operation Example (b)
TCNT_2 value
TCLKC
TCLKD
TCNT_2
TCNT_1
FFFD
Figure 10.22 Cascaded Operation Example (b)
Figure 10.21 Cascaded Operation Example (a)
H'0512
0000
FFFE
As I1AE in TICCR is 0, data is not captured in TGRA_2 at the TIOC1A input timing.
FFFF
H'0512
0000
H'0513
0001
0001
0002
H'0514
H'C256
H'0513
0001
0000
FFFF
0000
Time

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