r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 576

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
• Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing
• Examples of Output Waveform Control at Synchronous Counter Clearing in Complementary
Rev. 2.00 Dec. 09, 2005 Page 552 of 1152
REJ09B0191-0200
Figure 10.57 Example of Procedure for Setting Output Waveform Control at Synchronous
in Complementary PWM Mode
An example of the procedure for setting output waveform control at synchronous counter
clearing in complementary PWM mode is shown in figure 10.57.
PWM Mode
Figures 10.58 to 10.61 show examples of output waveform control in which the MTU2
operates in complementary PWM mode and synchronous counter clearing is generated while
the WRE bit in TWCR is set to 1. In the examples shown in figures 10.58 to 10.61,
synchronous counter clearing occurs at timing (3), (6), (8), and (11) shown in figure 10.56,
respectively.
In the MTU2S, these examples are equivalent to the cases when the MTU2S operates in
complementary PWM mode and synchronous counter clearing is generated while the SCC bit
is cleared to 0 and the WRE bit is set to 1 in TWCR.
synchronous counter clearing
synchronous counter clearing
Output waveform control at
complementary PWM mode
Output waveform control at
Stop count operation
Start count operation
Set TWCR and
Counter Clearing in Complementary PWM Mode
[1]
[2]
[3]
[1] Clear bits CST3 and CST4 in the timer
[2] Read bit WRE in TWCR and then write 1
[3] Set bits CST3 and CST4 in TSTR to 1 to
start register (TSTR) to 0, and halt timer
counter (TCNT) operation. Perform
TWCR setting while TCNT_3 and
TCNT_4 are stopped.
to it to suppress initial value output at
counter clearing.
start count operation.