r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 169

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

[Legend]
IRQ
Instruction (instruction replacing
interrupt exception handling)
First instruction in interrupt exception
service routine
m1:
m2:
m3:
F:
D:
E:
M:
Vector address read
Saving of SR (stack)
Saving of PC (stack)
Instruction fetch. Instruction is fetched from memory in which program is stored.
Instruction decoding. Fetched instruction is decoded.
Instruction execution. Data operation or address calculation is performed in accordance with the result of decoding.
Memory access. Memory data access is performed.
Figure 5.4 Example of Pipeline Operation when IRQ Interrupt is Accepted
2 Icyc + 3 Bcyc + 1 Pcyc
(No Register Banking)
Interrupt acceptance
F
D
3 Icyc
3 Icyc + m1 + m2
E
E
Rev. 2.00 Dec. 09, 2005 Page 145 of 1152
m1
M
Section 5 Interrupt Controller (INTC)
m2
M
m3
M
F
D
REJ09B0191-0200
E