r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 774

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.9
SCFCR resets the quantity of data in the transmit and receive FIFO data registers, sets the trigger
data quantity, and contains an enable bit for loop-back testing. SCFCR can always be read and
written to by the CPU. It is initialized to H'0000 by a power-on reset.
Initial value:
Rev. 2.00 Dec. 09, 2005 Page 750 of 1152
REJ09B0191-0200
Bit
15 to 11
10 to 8
R/W:
Bit:
FIFO Control Register (SCFCR)
Bit Name
—
RSTRG[2:0] 000
15
R
0
-
14
R
0
-
13
R
0
-
Initial
Value
All 0
12
R
0
-
11
R/W
R
R/W
R
0
-
R/W
10
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
RTS Output Active Trigger
When the quantity of receive data in receive FIFO data
register (SCFRDR) becomes more than the number
shown below, RTS signal is set to high.
000: 15
001: 1
010: 4
011: 6
100: 8
101: 10
110: 12
111: 14
RSTRG[2:0]
R/W
9
0
R/W
8
0
R/W
7
0
RTRG[1:0]
R/W
6
0
R/W
5
0
TTRG[1:0]
R/W
4
0
R/W
MCE
3
0
TFRST RFRST
R/W
2
0
R/W
1
0
LOOP
R/W
0
0