r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 201

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

(3)
(Example 3-1)
• Register specifications
BAR_0 = H'00314156, BAMR_0 = H'00000000, BBR_0 = H'0094, BAR_1= H'00055555,
BAMR_1 = H'00000000, BBR_1 = H'12A9, BDR_1 = H'78787878, BDMR_1 = H'0F0F0F0F,
BRCR = H'00000000
<Channel 0>
Address:
Bus cycle: I bus/instruction fetch/read (operand size is not included in the condition)
<Channel 1>
Address:
Data:
Bus cycle: I bus/data access/write/byte
On channel 0, the setting of I bus/instruction fetch is ignored.
On channel 1, a user break occurs when the DMAC writes byte data H'7x in address
H'00055555 on the I bus (write by the CPU does not generate a user break).
Break Condition Specified for I Bus Data Access Cycle
H'00314156, Address mask: H'00000000
H'00055555, Address mask: H'00000000
H'00000078, Data mask: H'0000000F
Rev. 2.00 Dec. 09, 2005 Page 177 of 1152
Section 6 User Break Controller (UBC)
REJ09B0191-0200